Modeling of Thermal Processing at the Formation of Shallow Doped IC Active Regions

Abstract

Physical and mathematical models as well as numerical algorithms for simulation of advanced technological processes, such as thermal annealing after low-energy ion implantation used during the VLSI fabrication are presented. In this paper we propose a model that treats the migration of the impurity atoms at the thermal annealing. We take into account process nonlinearity and inuence of non-uniform defects distribution as well as electric eld and elastic stress on the migration of atoms. The redistribution of point defects as well as the diusion of nonequilibrium impurity interstitials in silicon are described by time-dependent quasi-linear parabolic equations. The results of numerical calculations are presented as well.