Modeling of Power System Simulation Based on FRTDS

Jin, Zhengguo; Hu, Ruizhao; Tu, Sijia; Zhang, Jie; Jin, Xianglong; Guan, Ying; Zhu, Jie

doi:10.3390/en11102749

Cited by 9 publications

(16 citation statements)

References 13 publications

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“…Reference [13] added Generic Object Oriented Substation Event (GOOSE) and Sampled Value (SV) communication interfaces in FRTDS, which enables FRTDS to be used for real-time digital simulation of the intelligent substation. Reference [14] developed a set of power system electromagnetic transient simulation program generation tools that are compatible with the order flow so that users do not have to care about the simulation program. To alleviate the data storage pressure of FRTDS and improve the simulation calculation speed, the multi-value parameters which are required by the direct calculation method (not to solve the sub-network equation) are defined according to the sub-network, and the principles for dividing the sub-network of the large-scale power system is given in [15].…”

Section: Of 22mentioning

confidence: 99%

“…To alleviate the data storage pressure of FRTDS and improve the simulation calculation speed, the multi-value parameters which are required by the direct calculation method (not to solve the sub-network equation) are defined according to the sub-network, and the principles for dividing the sub-network of the large-scale power system is given in [15]. Reference [14] used the features of network symmetry and the same switch resistances and gave the multi-valued parameter compression storage method and the search method in hardware.…”

Section: Of 22mentioning

confidence: 99%

“…Obviously, the number of ʺ1ʺs in the influence word can determine the decoding method. The decoding method is used to reduce the amount of storage, and this has been studied in depth in [14]. Since FRTDS cannot deal with the "if-else" program, ferromagnetic coil inductance L can only be calculated by complex operations:…”

Section: Multi-value Parameter Querymentioning

confidence: 99%

“…Obviously, the number of "1"s in the influence word can determine the decoding method. The decoding method is used to reduce the amount of storage, and this has been studied in depth in [14].…”

Section: Timing Transmission Pathmentioning

confidence: 99%

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A New FPGA-Based Real-Time Digital Solver for Power System Simulation

Bingda

Jin

et al. 2019

Energies

Self Cite

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Considering the rational use of field programmable gate array (FPGA) resources, this paper proposes a new FPGA-based real-time digital solver (FRTDS) for power system simulation. Based on the relationship between the number of computing components, the operating frequency, and the pipeline length, the best selection principle is given. By analyzing the implementation method of the Multi-Port Read/Write Circuit, the computing formula of the Look-Up-Table (LUT) consumption was derived. Given the excessive use of LUTs in the original computing components, the computing components were assembled in a single typical arithmetic expression of the power system simulation program, as the basic computing formula was characterized by a subset of the typical computing formula and multiple uses of the same variable. Data communication between different computing components was realized by using Multi-Port Input Circuits that share some outputs of read controller, and Multi-Port Output Circuits, which share some outputs of computing cores. According to the test results of original FRTDS and new FRTDS, it was found that the solution proposed in this paper had a shorter ideal simulation time and a higher parallel computing capability, which was very suitable for real-time digital simulation of power systems.

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Section: Of 22mentioning

confidence: 99%

Section: Of 22mentioning

confidence: 99%

Section: Multi-value Parameter Querymentioning

confidence: 99%

Section: Timing Transmission Pathmentioning

confidence: 99%

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A New FPGA-Based Real-Time Digital Solver for Power System Simulation

Bingda

Jin

et al. 2019

Energies

Self Cite

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“…Hardware in the loop (HIL) real-time simulation of power electronics converters on field-programmable gate arrays (FPGA) has gained more attractiveness because it can meet challenges [1][2][3] relating to the more complex topology of power electronics converters and achieve a higher switching frequency, etc. [4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Hardware in the Loop Real-time Simulation for the Associated Discrete Circuit Modeling Optimization Method of Power Converters

Guo¹,

Yuan²,

Tang³

et al. 2018

Energies

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Due to the complicated circuit topology and high switching frequency, field-programmable gate arrays (FPGA) can stand up to the challenges for the hardware in the loop (HIL) real-time simulation of power electronics converters. The Associated Discrete Circuit (ADC) modeling method, which has a fixed admittance matrix, greatly reduces the computation cost for FPGA. However, the oscillations introduced by the switch-equivalent model reduces the simulation accuracy. In this paper, firstly, a novel algorithm is proposed to determine the optimal discrete-time switch admittance parameter, Gs, which is obtained by minimizing the switching loss. Secondly, the FPGA resource optimization method, in which the simulation time step, bit-length, and model precision are taken into consideration, is presented when the power electronics converter is implemented in FPGA. Finally, the above method is validated on the topology of a three-phase inverter with LC filters. The HIL simulation and practicality experiments verify the effect of FPGA resource optimization and the validity of the ADC modeling method, respectively.Another more general method to solve this problem is to select the optimal switch admittance parameter, Gs. One possibility is to consider a priori the switch admittance parameter, and then find the corresponding optimum value by comparing the offline simulation results with the benchmark results to minimize the relative errors; however, such a trial-and-error method has a low efficiency [19]. Within this context, the paper proposes a novel approach to choose the optimal switch admittance parameter, Gs, by minimizing the switching loss to reduce the computations required and increase the simulation precision.The high parallelism offered by FPGAs and their potential to conduct a real-time simulation in the nanosecond range make these devices an emerging processor for real-time simulation of a complex power electronic system [20][21][22][23][24]. However, due to the limited FPGA hardware resources, it is especially important to balance FPGA resource consumption and simulation accuracy. Theoretically, precise simulation results could be obtained by excessive bit-length, but it would cause unnecessary FPGA resource consumption [25,26]. Meanwhile, with the purpose of decreasing the discretization process error, the simulation time step should be set as small as possible; however, the quantization error caused by a small simulation time step may reduce the simulation accuracy [27]. Some scholars conducted a related qualitative analysis respectively but lacked overall quantitative calculations. Therefore, how to precisely select the bit-length and simulation time step is a valuable task that needs to be solved in the realm of HIL real-time simulation in FPGA. Additionally, High-Level Synthesis tools such as, Vivado High Level Synthesis (VHLS) and OpenCL SDK [28,29], allow the use of high-level languages to ease the burden of design and verification of hardware, which reduces the development time and difficulty and improves ...

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Parallel kernel solver of an FPGA‐based real‐time simulator for active distribution networks

Wang

et al. 2022

IET Renewable Power Gen

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Field‐programmable gate array (FPGA)‐based real‐time simulators are often applied in simulations of active distribution networks (ADNs) because of their parallel architectures and low cost. The overall performance of an FPGA‐based real‐time simulator is mainly determined by its kernel solver, which solves the nodal equation at each simulation time step. With the increasing scale of ADNs, real‐time simulations of fast switching dynamics, along with limited computation hardware, have increased the requirements of the solver in terms of both time and resource consumption. In this study, a highly parallel kernel solver is proposed to improve the simulation efficiency of the FPGA‐based real‐time simulator. The multi‐level parallel design and its implementation, including the parallelism at the system and module and element levels, are presented in detail. A modified IEEE 123‐node system with distributed photovoltaics (PVs) is then simulated using a three‐FPGA‐based real‐time simulator. Simulation results are compared with the commercial simulation tool PSCAD/EMTDC to validate the proposed kernel solver.

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Modeling of Power System Simulation Based on FRTDS

Cited by 9 publications

References 13 publications

A New FPGA-Based Real-Time Digital Solver for Power System Simulation

A New FPGA-Based Real-Time Digital Solver for Power System Simulation

Hardware in the Loop Real-time Simulation for the Associated Discrete Circuit Modeling Optimization Method of Power Converters

Parallel kernel solver of an FPGA‐based real‐time simulator for active distribution networks

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