Modeling of IGBT With High Bipolar Gain for Mitigating Gate Voltage Oscillations During Short Circuit

Abstract

In this paper, the impact of the PNP bipolar transistor gain on the short-circuit behaviour of High Voltage Trench IGBTs is analysed. The short circuit ruggedness against highfrequency oscillations is strongly improved by increasing the hole current supplied by the collector. By doing so, the electric field at the emitter of the IGBT is increased and less influenced by the amount of the excess charge (i.e., the electric field is fixed). The charge-field interactions during the short circuit event, leading to a periodic charge storage and charge removal effect and provoking miller capacitance variations, can be mitigated. The effectiveness of using IGBTs with high bipolar gain is validated through both simulations and experiments, also a design rule to trade off the IGBT's losses and short-circuit robustness is provided.

The Mechanism of Short-Circuit Oscillations in Automotive-Grade Multi-Chip Parallel Power Modules and an Effective Mitigation Approach

“…Among the different IGBT failure mechanisms under SC conditions, high-frequency gate voltage oscillations have been reported with various interpretations. Compared to single-chip modules, SC gate oscillations are more likely to occur in multi-chip parallel modules [8,9]. It is well known that IGBT chips are inherently unstable at high collector voltages and high temperatures due to the presence of negative gate capacitance [10][11][12][13], and efforts have been made to improve layout designs to suppress these oscillations [8,14,15].…”

Reliability Enhancement of Power IGBTs under Short-Circuit Fault Condition Using Short-Circuit Current Limiting-Based Technique

“…For the modern IGBTs, therefore, the advanced designs provide a homogeneously SCF current sharing between the device cells, and hence, less sensitivity to latch-up failure has been obtained. In the gate-oscillation, leading to gate-oxide breakdown, both gate circuit elements and structural factors play important roles, and specific design and implementation for gate-oscillations mitigation are required [26]. Structural modifications are also proposed for preventing self-turn-off and MOSFET modes [27].…”