Modeling, design, and performance analysis of a parallel hybrid data/command driven architecture system and its scalable dynamic load balancing circuit

Heath, J.R.; Ramamoorthy, Subramanian; Stroud, Charles E.; Hurt, A.D.

doi:10.1109/82.559366

Cited by 3 publications

(4 citation statements)

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“…The current study does not fully address the issue of scheduling under limited resources. In practical applications, it is imperative to consider the load balancing problem in dataflow execution 8 . The significant reduction in theoretical performance is a notable drawback of this approach.…”

Section: Introductionmentioning

confidence: 99%

HAD:A Prototype Of Dataflow Compute Architecture

Luo,

Zhao,

Wen

et al. 2024

Preprint

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To investigate the features, implementation, and applications of data flow architecture, a novel dataflow computing system, HAD (Hardware Accelerated Dataflow), is proposed. This system enhances the traditional control flow processor by integrating a dataflow component.HAD introduces two specialized instructions to the RISC ISA and provides OS system calls for applications. Users can execute programs that adhere to the dataflow execution model on the system, enabling synchronization and mutual exclusion between processes through the inherent characteristics of dataflow computing.We further analyze how our dataflow computing can reduce the overhead of OS system calls for synchronization and mutual exclusion between processes.Lastly, we perform simulations using Verilator, implement the system on an FPGA device based on the RISC-V prototype architecture, and transplant a miniature operating system for it. We evaluate its performance using EPCC Microbenchmarks. The simulation and physical experiment results indicate that when the number of processes is substantial, the system exhibits a time reduction of up to 29\% compared to the traditional approach. The simulation results closely correspond to the actual outcomes.

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Section: Introductionmentioning

confidence: 99%

HAD:A Prototype Of Dataflow Compute Architecture

Luo,

Zhao,

Wen

et al. 2024

Preprint

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“…Details of the format of control tokens are presented in [2,15,8,9]. The experimental prototype Q was designed to hold 128 control tokens.…”

Section: Queue (Q) Specificationsmentioning

confidence: 99%

“…An example of this type architecture is the reconfigurable parallel Hybrid DatdCommand Driven Architecture (HDCA) as presented in [2,15,8,9]. HDCA is a hybrid between a von-Neuman and dataflow architecture.…”

Section: Introductionmentioning

confidence: 99%

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Modeling, design, virtual and physical prototyping, testing, and verification of a multifunctional processor queue for a single-chip multiprocessor architecture

Heath

Tan²

Proceedings 12th International Workshop on Rapid System Prototyping. RSP 2001

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Email: heat h@en g r. U ky .ed U ,and rew-ta n7@ hotmai I .com Abstract Critical to run-time processor resource allocation, reconfiguration, and control of a reconfigurable heterogeneous single-chip multiprocessor architecture is a defined multifunctional queue required by each processor of the architecture. The multifunctional queue implements six functions required for control, resource allocation, and reconfiguration within the architecture. In addition to normal queue functionality of First In First Out (FIFO) operation and empty,@ll indicator, the multifunctional queue implements the additional non-common functions of indicating when queue depth has reached a programmable threshold level, it indicates queue occupancy level at all times, it continually indicates queue input rate over a programmable time interval, it continually indicates queue input rate change over a programmable time interval and it can implement a pseudo-RAM function.An analytic functional model of the queue is first presented then an organization, architecture and design is developed followed by the development of appropriate analytic real-time performance metrics for the queue.Both virtual and Field Programmable Gate Array (FPGA) based prototypes of the queue are then developed and used for functional, maximum frequency, and/or performance model testing resulting in verification of desired queue functionality and performance. A contribution of the queue is its functional versatility which would allow its use in computer architectures or processors other than the described target architecture.

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