Modeling, design and fabrication of ultra-thin and low CTE organic interposers at 40µm I/O pitch

Wu, Zihan; Nair, Chandrasekharan; Suzuki, Yuya; Liu, Fuhan; Smet, Vanessa; Foxman, Daniel; Mishima, Hideo; Furuya, Ryuta; Tummala, Rao

doi:10.1109/ectc.2015.7159608

Cited by 5 publications

(4 citation statements)

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“…Without C ES D , for short interconnect lengths, the power overhead of the low swing circuit is higher than the power dissipation of the full swing. In this case, the critical length at which the two circuits demonstrate equal energy consumption is the shortest for silicon interposers Interconnect technology Silicon interposer [18] Silicon interposer [6] Glass interposer [7] Organic interposer [8] Critical Figure 9: Energy efficiency for the glass interposer. and reaches up to 380 µm for glass and organic interposers.…”

Section: Resultsmentioning

confidence: 99%

“…However, since the RDL on top of interposers is usually larger, a second case with more realistic wire models is also considered [6], where SiO 2 is used as dielectric with relative dielectric permittivity ε r = 3.9. The parameters of the interconnects on a glass and organic interposer are derived from [7] and [8], respectively. An Ajinomoto Build-up Film (ABF) is used for the insulation of metal layers on the glass interposer, with ε r = 3.35.…”

Section: Interconnect Modelingmentioning

confidence: 99%

“…Hence, the capacitances of the bottom wires follow the closed-form expressions for S1, where only one ground plane is considered. The organic interposer of [8], is modeled in the exact same way as glass, due to the low permittivity (ε r = 4.4 [22]) of the organic materials. Alternatively, the silicon substrate, with ε r = 11.2 [22], is electrically modeled by a ground plane.…”

Section: Interconnect Modelingmentioning

confidence: 99%

“…This integration paradigm allows multiple dies to be integrated on both sides of the interposer and be connected through redistribution layers (RDL), allowing an interconnect pitch comparable to on-chip wires and several times smaller than Printed Circuit Board (PCB) traces. As silicon-based 2.5-D ICs have been commercialised [5], different materials for interposer substrates are developed, moving from standard silicon [6] to other alternatives, such as glass [7] and organic substrate [8], [9]. Although these materials exhibit lower conductivity and thus provide better insulation, the problem of high interconnect power remains crucial, due to additional load capacitance from Through Package Via (TPV) and bump bonding.…”

Section: Introductionmentioning

confidence: 99%

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Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies

Maragkoudaki

Mroszczyk

Pavlidis

2018

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures

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Interconnects often constitute the major bottleneck in the design process of low power integrated circuits (IC). Although 2.5-D integration technologies support physical proximity, the dissipated power in the communication links remains high. In this work, the additional power savings for interposer-based interconnects enabled by low swing signaling is investigated. The energy consumed by a low swing scheme is, therefore, compared with a full swing solution and the critical length of the interconnect, above which the low swing solution starts to pay off, is determined for diverse interposer technologies. The energy consumption is compared for three different substrate materials, silicon, glass, and organic. Results indicate that the higher the load capacitance of the communication medium is, the greater the energy savings of the low swing circuit are. Specifically, in cases that electrostatic discharge (ESD) protection is required, the low swing circuit is always superior in terms of energy consumption due to the high capacitive load of the ESD circuit, regardless the substrate material and the link length. Without ESD protection, the highest critical length is about 380 µm for glass and organic interposers. To further explore the limits of power reduction from low swing signaling for 2.5-D ICs, the effect of typical interconnect parameters such as width and space on the energy efficiency of low swing communication is evaluated.

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Section: Resultsmentioning

confidence: 99%