Modeling defect spatial distribution

Meyer, F.J.; Pradhan, Dhiraj K.

doi:10.1109/12.21146

Cited by 81 publications

(20 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Although other models have been suggested (e.g., [69]), we will concentrate in this paper on this family of distributions due to the ease of calculation when using the Poisson distribution, the relative ease of the integration (analytical or numerical) needed for the compounding, and the documented good fit of these distributions to empirical data [17].…”

Section: A the Poisson And Compound Poisson Yield Modelsmentioning

confidence: 99%

Defect tolerance in VLSI circuits: techniques and yield analysis

1998

View full text Add to dashboard Cite

show abstract

Section: A the Poisson And Compound Poisson Yield Modelsmentioning

confidence: 99%

Defect tolerance in VLSI circuits: techniques and yield analysis

1998

View full text Add to dashboard Cite

show abstract

“…These Markov chains assume the defects "arrive" in a random order, so it is most relevant for repair algorithms that process one defect at a time and get their defects in random order (or are not harmed by ordering). This is the same technique as that used in [4]. Contrast this with the methods of [2,6], which rely, for example, on fault trees.…”

Section: Yield Resultsmentioning

confidence: 99%

Simulation of reconfigurable memory core yield

Ottavi

Wang

Meyer

et al. 2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

We give a Markov chain model of the yield of an embedded memory core. The model allows easy inclusion of the effect of possible defects elsewhere on the chip that includes the embedded memory. We propose a reconfiguration algorithm for the case of both spare rows and columns that is simple enough that it could serve as built-in self-repair on the chip. Compared to an optimal configuration algorithm, there is no visible difference in the yield. We use parameters from an IBM embedded SRAM process to illustrate the yield calculation. We study the effect of different spare allocations. We conclude that as long as there is at least one spare of each type, the spares do not need to be balanced, once the yield impact of being part of a system-on-a-chip has been taken into account.

show abstract

“…Starting from (12), the second step of method A introduces the clustering effect that was not considered in the computation of Y r [by (11)]. λ r can be considered as the average number of faults left unrepaired after the first step; this is obtained by inverting the Poisson expression computed for k = 0, i.e., Y r = e −λ r .…”

Section: A Methods Amentioning

confidence: 99%

Evaluating the Yield of Repairable SRAMs for ATE

Ottavi

Schiano

Wang

et al. 2006

IEEE Trans. Instrum. Meas.

Self Cite

View full text Add to dashboard Cite

Abstract-An accurate yield evaluation is essential in selecting redundancy allocation and testing strategies for memories. Yield evaluation can resolve the many issues revolving around costeffective built-in self-test (BIST) and automatic test equipment (ATE)-based solutions for a higher test transparency. In this paper, two yield-calculation methodologies for SRAM arrays are proposed. General yield expressions for VLSI chips are initially presented. The regular and repetitive structure of an SRAM array is exploited, and substantial yield improvements can be achieved by the introduction of redundancy. Two repair yield-evaluation methods for one-dimensional redundant memory arrays are introduced and compared for ATE application. The first method is based on the sum of the probabilities of all repairable fault patterns; the second method is based on Markov modeling. Using industrial data, it is shown that these methods are applicable to ATE usage under different conditions of defect rate in the possible defects. Different features of the proposed methods are discussed.

show abstract

Modeling defect spatial distribution

Cited by 81 publications

References 16 publications

Defect tolerance in VLSI circuits: techniques and yield analysis

Defect tolerance in VLSI circuits: techniques and yield analysis

Simulation of reconfigurable memory core yield

Evaluating the Yield of Repairable SRAMs for ATE

Contact Info

Product

Resources

About