Modeling Attacks and Efficient Countermeasures on Interpose PUF

Adhithan, R. Raja; Anandakumar, N. Nalla

doi:10.1007/978-3-030-70881-8_10

Cited by 1 publication

(1 citation statement)

References 22 publications

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“…However, hardware cost of XOR PUF as well as the percentage of unstable responses exponentially increase with the increasing number of APUF components in an XOR PUF [31]. Moreover, in recent years, different variants of the modeling attacks have been reported to break XOR PUF architectures when given sufficient CRPs [23], [24], [25], [26], [29], [30], [31], [32], [33]. Several approaches have been introduced that utilize pre-extracted delay parameters to improve the security of XOR APUFs [32], [34], [35].…”

Section: Introductionmentioning

confidence: 99%

Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security

2022

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Physically unclonable functions (PUFs) are recently utilized as a promising security solution for authentication and identification of internet of things (IoT) devices. In this article, we present an efficient implementation of XOR Arbiter PUF (XOR APUF) on field-programmable gate arrays (FPGAs). In our work, we incorporated concept of discrete programmable delays logic (PDL) configurations, the obfuscated challenges and temporal majority voting (TMV) before the XOR operation concurrently to enhance uniqueness and security. The derived design has been verified on 25 Xilinx Artix-7 FPGAs and the results are promising with uniqueness of 48.69%, uniformity 50.73% and reliability 99.41%, which significantly improves over previous work into XOR APUF designs. In addition, we also investigate modeling attack resistance of the proposed design against various modelling attacks and the security analysis show that the proposed PUF has lower prediction rate (< 65%) when compared to the previous XOR APUF designs.INDEX TERMS Physical unclonable functions (PUFs), Internet of Things (IoT), programmable delays line (PDL), FPGA, XOR arbiter PUF (XOR APUF).

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