Modeling and verification of iterated systems and protocols

Abstract

The high complexip of modern hardware system necessitates the we of formal methods for checking the satisfiction of desired properties and the absence of design flaws. Some powerful methods such as model checking and the (LFautomata approach havefound wide acceptance, birr sufferfrom the "state explosion" problem. To avoid this issee we recently proposed a new formal verifcotion method based on series-parallel posetr. B e technique is applicable to verifiing the proper sequencing of events occurring in non-iterated. as well as globallyiterated~ocal!v-non-iterared systems. In this paper we extend the series-parallel poset verification to handle the much broader closs of general iterated svstems. This allows us to model and verz3 the behavior of systems involving feedback on multiple levels. as well a s the behavior of communication, interconnect. and cache coherence protocols. The ver$cation algorithms retain a low-orderpolynomialspace-and time complexip. INTRODUCTIONThe ever-increasing complexity of hardware systems and the protocols which govern their behavior has peatly increased the likelihood of design errors, and, at the same time, limited the usefulness of the classical simulation and testing methods for uncovering design faults. As a result the field of formal verification has rapidly developed into a major research effort to find more accurate and reliable methods for proving the correctness of hardware designs. An excellent overview of the field of formal verification can he found in [I]. Some powerful

Automatic generation of Chu space model expressions for verification

“…A number of interesting approaches have been proposed including Petri nets [17,18], Mazurkiewicz traces [15,16], series-parallel posets and pomsets [13,14,19,21,22,23], event structures [18], and higher dimensional automata [3,20]. The Chu space model of concurrent behavior was proposed by Vineet Gupta and Vaughan Pratt [1,2].…”