Modeling and Simulation of on-chip ramp generator for power management IC's using cadence

Sudharshan, K M; Pallavi, R; Anilkumar, C.S.; Yatheesh, H G

doi:10.1109/rteict42901.2018.9012344

2018 3rd IEEE International Conference on Recent Trends in Electronics, Information &Amp; Communication Technology (RTEICT) 2018

DOI: 10.1109/rteict42901.2018.9012344

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Modeling and Simulation of on-chip ramp generator for power management IC's using cadence

K M Sudharshan

R Pallavi

C.S. Anilkumar

et al.

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Modeling and Simulation of on-chip ramp generator for power management IC's using cadence

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References 3 publications

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