Modeling and Signal Integrity Analysis of 3D XPoint Memory Cells and Interconnections with Memory Size Variations During Read Operation

Son, Kyungjune; Cho, Kyungjun; Kim, Subin; Park, Gapyeol; Song, Ki-Il; Kim, Journ

doi:10.1109/emcsi.2018.8495304

Cited by 9 publications

(5 citation statements)

References 2 publications

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“…13 However, the undesired leakage current flowing through unselected cells in the 3D array will cause read errors. 15 To solve this problem, each PCM unit is in series with an OTS selector to suppress the sneak current and enable the large 3D stacking architecture. 16,17 An OTS selector is a volatile switching device and its switching characteristic is driven by external voltage excitation.…”

Section: Introductionmentioning

confidence: 99%

“…In the meantime, selectors need to be turned on and off during the operation of PCMs and the endurance of selectors should be much more than that of PCMs to ensure a long memory chip life. 15,32 When OTS selectors switch on, the large on-current flowing will cause heat accumulation and can be extremely severe as the cycles increase. For OTS selectors with low thermal stability, the heat effect on OTS materials will be significant and is harmful to device performance.…”

Section: Introductionmentioning

confidence: 99%

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A refresh operation method for solving thermal stability issues and improving endurance of ovonic threshold switching selectors

et al. 2023

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A refresh operation method for solving thermal stability issues and improving endurance of ovonic threshold switching selectors

et al. 2023

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“…2(b) shows the electrical model of PCM cell. The resistance across the PCM cell can be modeled by two voltage controlled switches [7]. Depending on the status of switches S 1 and S 2 , different currents flow between two lines connected to the terminals of the PCM cell, determined by G A and G C .…”

Section: Introductionmentioning

confidence: 99%

Exploring the Feasibility of Using 3-D XPoint as an In-Memory Computing Accelerator

Zabihi

Resch

Cılasun

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This paper describes how 3D XPoint memory arrays can be used as in-memory computing accelerators. We first show that thresholded matrix-vector multiplication (TMVM), the fundamental computational kernel in many applications including machine learning, can be implemented within a 3D XPoint array without requiring data to leave the array for processing. Using the implementation of TMVM, we then discuss the implementation of a binary neural inference engine. We discuss the application of the core concept to address issues such as system scalability, where we connect multiple 3D XPoint arrays, and power integrity, where we analyze the parasitic effects of metal lines on noise margins. To assure power integrity within the 3D XPoint array during this implementation, we carefully analyze the parasitic effects of metal lines on the accuracy of the implementations. We quantify the impact of parasitics on limiting the size and configuration of a 3D XPoint array, and estimate the maximum acceptable size of a 3D XPoint subarray.

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“…There have been some speculations on 3D Xpoint [2], which reveals a glimpse of new high-performance secondary storage. However, the materials and techniques used in the products remain unknown [3]. As a result, this paper explores the possibility of developing a solid state drive (SSD) based on byte-addressable NVM (BNVM-SSD) instead of NAND flash memory for secondary storage.…”

Section: Introductionmentioning

confidence: 99%

Address Translation Layer for Byte-Addressable Non-Volatile Memory-Based Solid State Drives

Kwon

2019

IEEE Access

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Because of the need for processing and managing the massive amounts of big data in smart/wearable devices and driverless vehicles, semiconductor companies are focusing on developing byte-addressable non-volatile memory (NVM)-based storage systems. The byte-addressable NVMs, such as phase-change memory, resistive memory, and magnetoresistive memory, are regarded as an alternative to NAND flash memories. There have been many proposals and studies on the use of NVM as main memory in the memory hierarchy. However, there has not been much academic research on using NVM as a substitute for NAND flash memories. This paper provides a system architecture for an NVM-based solid state drive based on some speculations/assumptions on the hardware characteristics of NVMs. It applies the previously proposed address-mapping algorithms of conventional solid state drives to the NVM-based solid state drives and examines their suitability. The optimization of I/O parallelism of static and dynamic address mapping algorithms is compared and analyzed. This paper also observes the effect of log block policies on the hardware characteristics of the NVMs.

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Modeling and Signal Integrity Analysis of 3D XPoint Memory Cells and Interconnections with Memory Size Variations During Read Operation

Cited by 9 publications

References 2 publications

A refresh operation method for solving thermal stability issues and improving endurance of ovonic threshold switching selectors

A refresh operation method for solving thermal stability issues and improving endurance of ovonic threshold switching selectors

Exploring the Feasibility of Using 3-D XPoint as an In-Memory Computing Accelerator

Address Translation Layer for Byte-Addressable Non-Volatile Memory-Based Solid State Drives

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