Modeling and optimized design of current mode MUX/XOR and D flip-flop

Performance Evaluation of Multiple-Bit Delay Detection with Majority Vote Decision Rule in Optical DPSK Systems

“…In this method, based on each r i , an individual and independent decision is made in each delay branch, and the final decision for decoding d M is performed by selecting the decision that has been made most among all the M individual branches. So in majority vote detection, soft post-processing is avoided and consequently, the required electronic circuits is realizable by simple high speed mixed signal logic gates such as current-mode logic (CML) circuits [18]. It should be noted that multiplication of two bipolar signals followed by a zero threshold slicer is the same as using an XOR logic gate operating on the binary equivalent of the signals [6].…”

Design Techniques for Low-Power Cascaded CML Gates

“…1, where the npn network consists of emitter-coupled pairs implementing a given logic function, and a current I SS is steered to one of the two output branches according to the input values. As demonstrated in [10]- [11], the delay τ PD of a generic CML gate can be expressed as a function of its bias current according to the following general law …”

“…Actual CML circuits are made up of cascaded gates, thus results in [7]- [11] cannot immediately applied to practical design. Moreover, due to the high complexity of typical circuits, the design procedure based on iterated simulations (with a trial-and-error approach or resorting to an Optimizer CAD tool) is unfeasible, since it is very time consuming and requires a very high computational effort.…”

“…inverter, XOR gate) [7]- [11]. At the best of the authors' knowledge, general techniques to manage the power-delay trade-off in single CML gates are developed only in [10]- [11].…”

“…The design procedure starts from the analytical delay model proposed by the same authors in [10]- [11], and in the considered design cases leads to analytical expressions of the bias currents, which are simple enough to be evaluated in a pencil and paper approach. Design examples are provided to clarify and validate the procedure, whose results are compared with simulations performed on a 20-GHz bipolar process.…”