Modeling and improving locality for the sparse-matrix–vector product on cache memories

Heras, Dora B.; Blanco, Vicente; Dominguez, Jessica A.; Rivera, Francisco F.

doi:10.1016/s0167-739x(00)00075-3

Cited by 16 publications

(8 citation statements)

References 21 publications

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“…Serial processing optimization was focused, since it is expected that the local processor improvements are spread to multiprocessor systems [14]. Some additional devices were investigated, namely: loop unrolling, loop splitting in chunks and memory sharing (by residual vector) during right-hand side evaluations [16].…”

Section: Discussionmentioning

confidence: 99%

Performance comparison of data-reordering algorithms for sparse matrix–vector multiplication in edge-based unstructured grid computations

Coutinho

Martins

Sydenstricker

et al. 2006

Int. J. Numer. Meth. Engng

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SUMMARYSeveral performance improvements for finite-element edge-based sparse matrix-vector multiplication algorithms on unstructured grids are presented and tested. Edge data structures for tetrahedral meshes and triangular interface elements are treated, focusing on nodal and edges renumbering strategies for improving processor and memory hierarchy use. Benchmark computations on Intel Itanium 2 and Pentium IV processors are performed. The results show performance improvements in CPU time ranging from 2 to 3.

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Section: Discussionmentioning

confidence: 99%

Performance comparison of data-reordering algorithms for sparse matrix–vector multiplication in edge-based unstructured grid computations

Coutinho

Martins

Sydenstricker

et al. 2006

Int. J. Numer. Meth. Engng

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“…Regarding the SpMV operation, the data layout (storage format) depends on the sparsity pattern of the matrix [23]. The most widely used format is known as Compressed Sparse Row (CSR).…”

Section: Intra-device Optimizationmentioning

confidence: 99%

Efficient CFD code implementation for the ARM-based Mont-Blanc architecture

Oyarzun

Borrell

Gorobets

et al. 2018

Future Generation Computer Systems

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h i g h l i g h t s• Termo Fluids CFD code has been run on up to 128 ARM-based Mont-Blanc nodes.• An heterogeneous implementation has been developed to occupy the overall system.• A dynamic Tabu search load balance algorithm distributes the workload among devices.• The hybrid approach is up to times faster than the CPU-only version of the code.• Mont-Blanc nodes are 41% more energy efficient than Minotauro hybrid nodes. t r a c tSince 2011, the European project Mont-Blanc has been focused on enabling ARM-based technology for HPC, developing both hardware platforms and system software. The latest Mont-Blanc prototypes use system-on-chip (SoC) devices that combine a CPU and a GPU sharing a common main memory. Specific developments of parallel computing software and well-suited implementation approaches are of crucial importance for such a heterogeneous architecture in order to efficiently exploit its potential. This paper is devoted to the optimizations carried out in the TermoFluids CFD code to efficiently run it on the Mont-Blanc system. The underlying numerical method is based on an unstructured finite-volume discretization of the Navier-Stokes equations for the numerical simulation of incompressible turbulent flows. It is implemented using a portable and modular operational approach based on a minimal set of linear algebra operations. An architecture-specific heterogeneous multilevel MPI+OpenMP+OpenCL implementation of such kernels is proposed. It includes optimizations of the storage formats, dynamic load balancing between the CPU and GPU devices and hiding of communication overheads by overlapping computations and data transfers. A detailed performance study shows time reductions of up to 2.1× on the kernels' execution with the new heterogeneous implementation, its scalability on up to 128 MontBlanc nodes and the energy savings (around 40%) achieved with the Mont-Blanc system versus the highend hybrid supercomputer MinoTauro.

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“…In the context of SPARSITY, Moon, et al, have applied this idea to the SPARSITY benchmark suite, showing speedups over conventional register blocking of up to 1.5× on Matrices 17, 20, 21, and 40. Heras, et al, have also proposed TSP-based reordering schemes, with an emphasis on theoretical aspects of formulating the problem [13]. Open issues include when to apply TSP-based reordering, what approximation heuristics are likely to work best, and what the run-time costs will be.…”

Section: Related Workmentioning

confidence: 99%

Fast sparse matrix-vector multiplication by exploiting variable block structure

Vuduc¹,

Moon²

2005

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We improve the performance of sparse matrix-vector multiply (SpMV) on modern cache-based superscalar machines when the matrix structure consists of multiple, irregularly aligned rectangular blocks. Matrices from finite element modeling applications often have this kind of structure. Our technique splits the matrix, A, into a sum, A 1 + A 2 + . . . + A s , where each term is stored in a new data structure, unaligned block compressed sparse row (UBCSR) format . The classical alternative approach of storing A in a block compressed sparse row (BCSR) format yields limited performance gains because it imposes a particular alignment of the matrix non-zero structure, leading to extra work from explicitly padded zeros. Combining splitting and UBCSR reduces this extra work while retaining the generally lower memory bandwidth requirements and register-level tiling opportunities of BCSR. Using application test matrices, we show empirically that speedups can be as high as 2.1× over not blocking at all, and as high as 1.8× over the standard BCSR implementation used in prior work. When performance does not improve, split UBCSR can still significantly reduce matrix storage.Through extensive experiments, we further show that the empirically optimal number of splittings s and the block size for each matrix term A i will in practice depend on the matrix and hardware platform. Our data lay a foundation for future development of fully automated methods for tuning these parameters.

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Modeling and improving locality for the sparse-matrix–vector product on cache memories

Cited by 16 publications

References 21 publications

Performance comparison of data-reordering algorithms for sparse matrix–vector multiplication in edge-based unstructured grid computations

Performance comparison of data-reordering algorithms for sparse matrix–vector multiplication in edge-based unstructured grid computations

Efficient CFD code implementation for the ARM-based Mont-Blanc architecture

Fast sparse matrix-vector multiplication by exploiting variable block structure

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