Modeling and Evaluation of Positive-Feedback Source-Coupled Logic

Abstract

Positive feedback source-coupled logic (PFSCL) is proposed as an alternative logic style to traditional SCL logic, which is often used in high-resolution mixed-signal integrated circuits. Positive feedback allows for significantly reducing the NMOS transistors' aspect ratio compared to traditional single-ended SCL gates for equal values of design constraints. The resulting reduction in NMOS parasitic capacitances permits a significant speed up, which can be traded off to achieve a power saving for a given speed constraint, as well as a silicon area reduction. PFSCL gates are analytically modeled in terms of their static parameters and delay, which are expressed as a function of bias current, transistors' aspect ratios and process parameters. Spectre simulations by using a 0.35-μm CMOS process confirm that the proposed models are sufficiently accurate in practical cases. PFSCL gates are also compared with traditional SCL circuits by resorting to two different metrics: the gate delay in a Ring Oscillator and that of an inverter with a fan-out of 4. The comparison confirms that PFSCL logic is faster than SCL logic in most cases, and design conditions leading to a speed advantage are identified. As a result, PFSCL gates are an interesting alternative to traditional SCL circuits in mixed-signal applications requiring a high speed or a good balance with power dissipation

New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

“…It consists of a source-coupled nMOS transistor pair, M1-M2 biased by the constant current source, I ss and a pMOS load transistor M3 [8][9][10][11][12]. The output of the gate is taken from the drain of pMOS active load, M3.…”

“…The low gate output turns off transistor M3 through positive feedback. The (optional) pMOS transistor M5 is inserted to generate the complement of the output, and is substituted by a short circuit when it is not needed [9]. The above NOR gate topology has low transistor count as compared to source-coupled gates.…”

“…The above NOR gate topology has low transistor count as compared to source-coupled gates. The NOR gate topology can be extended to implement NAND gate by using De Morgan law and then taking the output from the drain of optional pMOS transistor (M5) [9] as shown in Figure 2(b).…”

“…Among the possible topologies, PFSCL is the most suitable logic style for designing systems with optimum balance between speed and power dissipation [8][9][10][11][12]. A PFSCL style is derived from the single-ended source-coupled logic in which a positive feedback is introduced that significantly increases the speed as compared to traditional SCL circuits [8].…”

“…A PFSCL style is derived from the single-ended source-coupled logic in which a positive feedback is introduced that significantly increases the speed as compared to traditional SCL circuits [8]. This improvement in speed can be traded off to reduce the power consumption of the circuits [9][10][11]. Thus, this logic style can be easily adopted in the design of high speed and high computing circuits for portable devices.…”