Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration

Xu, Zheng; Beece, Adam; Rose, Kenneth; Zhang, Tong; Lü, Jian–Qiang

doi:10.1109/3dic.2009.5306543

Cited by 34 publications

(8 citation statements)

References 7 publications

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“…In the meantime, the emerging 3D integration technology that stacks functional integrated circuit blocks horizontally with signal and power travel vertically to device strata through short interconnects e.g. TSV was found to be one of the key enabling technologies to accomplish highly compact electronic device with greater functionality and performance [1], [2]. Figure 1 illustrates an implementation of TSV technology that has been widely adopted in the 3D packaging industry.…”

Section: Introductionmentioning

confidence: 99%

Signal integrity study of high density through silicon via (TSV) technology

Cheah

Kong

Chew

et al. 2013

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

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This paper explores the electrical performance of several multi-channel TSV designs i.e. cross-etched full-plated TSV and cross-etched partial-plated TSV to further improve data transmission bandwidth among the vertically stacked silicon devices. The electrical characteristics of the multi-channel TSV designs were investigated and compared against the conventional TSV design in terms of return loss, insertion loss, near-end (NEXT) and far-end (FEXT) crosstalk. Fullwave electromagnetic simulation data showed the insertion loss performance of the multi-channel TSV designs are at par with the conventional TSV design up-to 50GHz. Meanwhile, the multi-channel TSV designs were found yielding improved NEXT and FEXT crosstalk performance. Transient analyses of respective TSV designs are also included in this paper for more conclusive discussions.

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Section: Introductionmentioning

confidence: 99%

Signal integrity study of high density through silicon via (TSV) technology

Cheah

Kong

Chew

et al. 2013

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

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“…Unlike preceding results [10], coaxial TSVs are not sensitive to silicon substrate resistivity [ Fig. 2(c)].…”

Section: Coaxial Tsv Parametric Analysismentioning

confidence: 84%

Three-Dimensional Coaxial Through-Silicon-Via (TSV) Design

Lü

2012

IEEE Electron Device Lett.

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Being one of the most attractive 3-D integration solutions, through-silicon-vias (TSVs) electrically connect multiple strata of integrated circuits and/or devices in a vertical fashion. This paper examines the electrical performance of coaxial TSV, which is a new configuration that offers better signal integrity than other TSV structures. Various processing materials and physical geometries are considered for coaxial TSV designs. The full-wave extraction and empirical calculations show good agreement in TSV passive elements (RLGC). Latency, power, and crosstalk are evaluated and compared between coaxial TSVs and common signal-ground (S-G) paired TSVs. Furthermore, a wideband SPICE model is established to well fit the coaxial TSV fullwave solution, facilitating 3-D system design and evaluation.

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“…As a result, silicon-to-silicon integration is becoming an important 3D packaging technique. Especially with the emergence of through silicon via (TSV) technology, 3D packaging provides a robust wafer level device stacking platform that enables 3D die to wafer integration [3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

Li¹,

Lee²,

Lewis³

et al. 2010

Journal of Microelectronics and Electronic Packaging

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The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity.No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underflll process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underflll reflow proflle study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material. Keywords-Noflow underflll, flip chip, wafer level packaging, silicon to/on silicon, chip floating, underfill voiding

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Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration

Cited by 34 publications

References 7 publications

Signal integrity study of high density through silicon via (TSV) technology

Signal integrity study of high density through silicon via (TSV) technology

Three-Dimensional Coaxial Through-Silicon-Via (TSV) Design

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

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