Modeling and estimation of power supply noise using linear programming

Firouzi,; Kiamehr,; Tahoori,

doi:10.1109/iccad.2011.6105382

Cited by 8 publications

(4 citation statements)

References 15 publications

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“…Voltage droop, which has been shown to vary significantly over time and from gate to gate [Firouzi et al 2011;Ye et al 2014], significantly affects BTI-induced delay degradation [Wang et al 2007;Bhardwaj et al 2006]. According to Nassif [2008], the power network can be modeled as a resistive network distributed over the die (see Figure 3).…”

Section: Voltage-droop Featurementioning

confidence: 99%

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection

Firouzi

Chakrabarty

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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Process together with runtime variations in temperature and voltage, as well as transistor aging, degrade path delay and may eventually induce circuit failure due to timing variations. Therefore, in-field tracking of path delays is essential, and to respond to this need, several delay sensor designs have been proposed in the literature. However, due to the significant overhead of these sensors and the large number of critical paths in today's IC, it is infeasible to monitor the delay of every critical path in silicon. We present an aging-and variationaware representative path selection technique based on machine learning that allows to measure the delay of a small set of paths and infer the delay of a larger pool of paths that are likely to fail due to delay variations. Simulation results for benchmark circuits highlight the accuracy of the proposed approach for predicting critical-path delay based on the selected representative paths.

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Section: Voltage-droop Featurementioning

confidence: 99%

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection

Firouzi

Chakrabarty

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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“…It has been shown in previous publications that any logic function can be described by a set of zero-one linear equations [5] [6]. For example an inverter with input and output can be expressed as 1…”

Section: Constraints Generationmentioning

confidence: 99%

On pattern generation for maximizing IR drop

Vijayakumar

Patil

Paladugu

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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Increase in power density and decrease in supply voltage results in greater power supply current. With scaling, line resistance increases. Together with increase in supply current, this results in ever larger IR drop in supply voltage. IR drop analysis is an important element of power supply network design. Maximizing IR drop is also an important component of manufacturing testing. As a CMOS gate primarily draws current during switching, IR drop maximization problem is akin to finding input pattern pair that maximizes circuit switching taking the drive strengths of the gates and their spatial distribution into consideration. In this paper, we examine IR-drop analysis problem for combinational circuits. The solution to the general problem of maximizing IR drop of a power supply network can be reformulated as a pattern generation problem to maximize IR drop at a specific point on the power supply network, as this analysis can then be applied on a collection of target points determined by load distribution on the grid. The main contributions of this paper are (i) formulation of objective function for pattern generation using the spatial location and strengths of the gates and (ii) expressing the Boolean relationships between gates to use in an Integer Linear Programming solver for solving the pattern generation problem. We further show that by exploiting the conic structure of combinational circuits and the proposed formulation of objective function, the technique is easily applied to larger circuits. The proposed technique was applied to ISCAS-85 benchmark circuits and validated in simulation. Results show that with targeted pattern generation and deterministic approach, we achieve ~25 % moreIR drop over random patterns on an average, while average run-time improves by four orders of magnitude.

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“…Modeling the Boolean relation in logic blocks as linear equations for similar maximization problems have been proposed in previous publications [2] [3]. Let us consider a logic block synthesized with inverter, 2-input NOR and 2-input NAND gates.…”

Section: Problem Formulationmentioning

confidence: 99%

“…Finding input vector to maximize the intrinsic capacitance of logic block is similar to other maximization problems discussed in literature, such as maximizing supply current, leakage current and crosstalk noise [2] [3]. Typical solution involves domain specific modeling for simplifying the search space or a genetic algorithm approach that rely primarily on simulation, coupled with heuristic input pattern modification using crossover and mutation [5].…”

Section: Introductionmentioning

confidence: 98%

On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery

Vijayakumar

Patil

Kundu

2014

2014 IEEE Computer Society Annual Symposium on VLSI

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The Intrinsic capacitance of CMOS circuits provides inexpensive decoupling capacitance for power supply noise mitigation. In FinFET circuits, such capacitance has greater dependence on the logic states of gates. Consequently, when a group of gates are inactive, there exists a combination of inputs that will maximize the decoupling capacitance for the power supply. In this paper, (i) we establish the input dependence of decoupling capacitance in FinFET circuits based on simulation results and (ii) propose a pattern generation solution to find an input pattern that maximizes such capacitance. This analysis is potentially important for circuit initialization in sleep states and in design planning for power delivery networks. The exact pattern generation problem is known to be computationally intractable. To reduce the order of computation, we propose simplification to the state dependent capacitance model that preserves accuracy while greatly reducing the amount of computation. The pattern generation problem is formulated as an Integer Linear Programming (ILP) problem. We evaluate the proposed solution on ISCAS-85 benchmark circuits. This approach is shown to be superior than random pattern simulation based solution. The scalability of the solution is improved via constraint-objective model order reduction and modeling at a higher level.

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Modeling and estimation of power supply noise using linear programming

Cited by 8 publications

References 15 publications

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection

On pattern generation for maximizing IR drop

On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery

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