Modeling and characterization of a 5.2 GHz VCO for UWB applications in 0.13 μm CMOS process

Abstract

This paper describes a 5.2 GHz voltage-controlled oscillator (VCO) as a key component in RF transceivers. The circuit includes a complementary crosscoupled MOSFET as a negative conductance, beside a tank circuit which consists of an optimal on-chip spiral inductor (L), and an accumulation mode MOS varactor (C(V)). A model for phase noise and figure merit is introduced and verified through simulation in a standard 0.13 lm CMOS process. The VCO core drew a 4.2 mA of current from a 1.2 V power supply and a phase noise of -98.5 dBc/Hz at 1 MHz offset from the 5.2 GHz carrier was calculated. The whole performance of the circuit specifically the tuning range was found to be 26%.

Layout Design of LC VCO with Current Mirror Using 0.18 µm Technology

“…Maximum d.c power dissipation = V supply × I bias (5) A figure of Merit is a quantity used to characterize the performance of a VCO relative to other VCOs' of the same type. The power, phase noise, frequency of oscillation, offset from carrier tradeoffs all are taken in the FOM value [3]:…”

“…Wireless standards specify the minimum level of the received signal, the maximum level of noise, the channel bandwidth, and the spacing between adjacent channels. Therefore, the maximum amount of acceptable phase noise on the oscillator can be calculated using the required signal to noise ratio after down conversion [3,4]. This paper presents a novel VCO architecture that can achieve low phase noise, low power consumption and enlarged tuning range.…”