Modeling and Analysis of Signal Integrity of High-Speed Interconnected Channel With Degraded Contact Surface

Wang, Ziren; Gao, Jinchun; Flowers, George T.; Wu, Yongle; Xie, Gang; Lv, Yinghua

doi:10.1109/tcpmt.2019.2920918

Cited by 10 publications

(4 citation statements)

References 17 publications

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“…Similarly, if Equation 14is equal to zero, then b 3 = −b 1 when the differential signal a d1 is input into the differential network, which require the reflection and NEXT parameters of one channel are equal to those of the other channel, that is, |S 11 − S 33 | and |S 31 − S 13 | are equal to zero. Accordingly, combining the physical meanings of Equations (13) and 14, the parameter d is defined.…”

Section: Symmetry Evaluation Of Differential Circuitsmentioning

confidence: 99%

“…Equations (13) and (14) contain many physical meanings. For example, inspection of Equation 13, it shows that when the differential signal a d1 is input into a differential network, the common-mode signal at the differential output port is related to the wave b 2 and b 4 of the equivalent single-ended network.…”

Section: Symmetry Evaluation Of Differential Circuitsmentioning

confidence: 99%

“…In literature 13, an electromagnetic numerical model and a distributed parameter circuit model were developed for differential channels with degraded connectors. In this work, considering the influence of signal transmission, reflection and crosstalk on differential circuit symmetry, the d parameter was defined for evaluating circuit symmetry.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Symmetry degradation of differential circuits induced by uneven gold plating of high‐speed connectors in extreme environment

Wang

Gao

Tian

et al. 2020

Micro & Optical Tech Letters

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High-speed connectors are widely used in digital differential circuits. Because of the uneven gold plating, the thin gold plating area on the contact surface of the connector will form corrosion films in extreme environment, which may not only deteriorate the reflection and transmission performance of electromagnetic wave in differential circuits but also affects its symmetry, which results in poor communication quality. In this work, considering the influence of differential circuit symmetry on the signal transmission, reflection and crosstalk, the d parameter was defined for measuring the circuit symmetry. The impact of high-speed connector degradation on symmetry of differential circuits was studied by both experimental investigation and electromagnetic numerical calculation model analysis. These results are helpful in developing a better understanding of impact of connector degradation on symmetry of high-speed differential circuits and in identifying failure features in fault diagnosis.

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Section: Symmetry Evaluation Of Differential Circuitsmentioning

confidence: 99%

Section: Symmetry Evaluation Of Differential Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Symmetry degradation of differential circuits induced by uneven gold plating of high‐speed connectors in extreme environment

Wang

Gao

Tian

et al. 2020

Micro & Optical Tech Letters

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“…This can worse transmission performance and even cause the system to fail. Therefore, the signal integrity problem has become more and more prominent [3], making it a critical concern for communication engineers and circuit designers.…”

Section: Introductionmentioning

confidence: 99%

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

Zhan,

Li,

Zou

et al. 2023

Electronics

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A high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) was implemented to mitigate decision feedback equalizer (DFE) error propagation in a 400 G Ethernet Serializer–Deserializer (SerDes) interface. Based on the SerDes interface link architecture with 5-tap DFE, the performance of the PBM under DFE error propagation was simulated theoretically, which could obtain an interleaving gain of 0.35 dB. In the pre-interleaver, in order to significantly increase the transmission rate while keeping the larger interleaving depth, characteristic polynomial parallelization with the logic expansion method and register-based memory with interleaving technology were adopted. Finally, the pre-interleaver was fabricated with 65 nm CMOS technology, with a total area of 0.615 mm2, including the I/O pad. The measurement results show that the horizontal opening degree of the output signal can reach 0.925 UI at the data rate of 41.6 Gb/s. The total power consumption is 38.52 mW at the supply voltage of 1.2 V and frequency of 1.3 GHz.

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Application of spatial filtering high order FDTD method in the multi-physics field coupled equations

Xie,

Pan,

Feng

et al. 2024

Computer Physics Communications

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Modeling and Analysis of Signal Integrity of High-Speed Interconnected Channel With Degraded Contact Surface

Cited by 10 publications

References 17 publications

Symmetry degradation of differential circuits induced by uneven gold plating of high‐speed connectors in extreme environment

Symmetry degradation of differential circuits induced by uneven gold plating of high‐speed connectors in extreme environment

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

Application of spatial filtering high order FDTD method in the multi-physics field coupled equations

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