Modeling, Analysis, and Implementation of Streaming Applications for Hardware Targets

Ravindran, Kaushik; Ghosal, Arkadeb; Limaye, Rhishikesh; Kim, Douglas S.; Andrade, Hugo A.; Correll, J.E.; Kornerup, Jacob; Wong, Ian; Wang, Gerald; Yang, Guang; Ekbal, Amal; Trimborn, Mike; Prasad, Ankita; Tran, Trung N.

doi:10.1007/978-1-4614-3879-3_2

Cited by 1 publication

(1 citation statement)

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“…Furthermore, LabView supports FPGA design using an SDF model with access patterns (SDF-AP). The LabView hardware implementation prototypes using the SDF-AP model are discussed in [10,13,14,36] where the experimental results indicate that SDF-AP model can reduce the buffer size requirements by about 63%. However, generating the FPGA code from these supported dataflow models relies on correct-by-design approach which does not provide conformance analysis of the hardware design.…”

Section: Labviewmentioning

confidence: 99%

Automatic Configurable Hardware Code Generation for Software-Defined Radios

2018

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The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the designer is experienced with hardware design. These low-level difficulties include non-standard interfacing methods, component communication and synchronization challenges, complicated timing constraints and processing blocks that need to be customized through time-consuming design tweaks. In this paper, we present a methodology for automated and behavioral integration of dedicated IP cores for rapid prototyping of SDR applications. To maintain high performance of the SDR designs, our methodology integrates IP cores using characteristics of the dataflow model of computation (MoC), namely the static dataflow with access patterns (SDF-AP). We show how the dataflow is mapped onto the low-level model of hardware by efficiently applying low-level based optimizations and using a formal analysis technique that guarantees the correctness of the generated solutions. Furthermore, we demonstrate the capability of our automated hardware design approach by developing eight SDR applications in VHDL. The results show that well-optimized designs are generated and that this can improve productivity while also conserving the hardware resources used.

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Section: Labviewmentioning

confidence: 99%