Modeling an Asynchronous Microprocessor

Abstract

Synchronous very large-scale integration (VLSI) design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Recently, there has been a resurgence of interest in asynchronous design techniques due to the significant potential benefits that the elimination of global synchronization may offer to issues such as clock distribution, power consumption, performance, and modularity. Modeling and simulation may perform a catalytic role in the quest for the realization of the potential offered by asynchronous logic. Hence, the recurrence of interest in asynchronous design has been accompanied by intense research activity aimed at developing notations and techniques appropriate for modeling and simulating asynchronous systems. Communication sequential processes and its executable counterpart, occam, are increasingly advocated as particularly suitable for this purpose. This article discusses the modeling of an asynchronous microprocessor using occam.

A Framework for Distributed Simulation of Asynchronous Handshake Circuits

“…Delays in one module may often be masked by occasional longer delays in another module, while the accumulation of delays through a chain reaction in a non-deterministic concurrent environment may have a chaotic effect on system performance. The need to evaluate the asynchronous architecture for different sub-system delays further complicates the process rendering simulation speed a crucial element [19].…”