Modeling adaptive streaming applications with parameterized polyhedral process networks

Abstract

The Kahn Process Network (KPN) model is a widely used modelof-computation to specify and map streaming applications onto multiprocessor systems-on-chips. In general, KPNs are difficult to analyze at design-time. Thus a special case of the KPN model, called Polyhedral Process Networks (PPN), has been proposed to address the analyzability issue. However, the PPN model is not able to capture adaptive/dynamic behavior. Such behavior is usually expressed by using parameters which values are reconfigured at run-time. To model the adaptive/dynamic applications, in this paper we introduce an extension of the PPN model, called Parameterized Polyhedral Process Networks (P 3 N), which still provides design-time analyzability to some extent. We first formally define the P 3 N model and its operational semantics. In addition, we devise a design-time analysis to extract relations between parameters. Based on the analysis, we propose an approach to ensure that consistent execution of the P 3 N model is preserved at run-time. Using an FPGA-based MPSoC platform, we present a performance evaluation of the possible overhead caused by the run-time reconfiguration.

Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs

“…Brook only handles kernels with affine bounds, and thus cannot be used for variable image sizes inducing exponential bounds. More generally, the same problem arises for all models relying on polyhedral analysis [6], as the Polyhedral Process Network (PPN) [22], a parameterized extension of it [26], or the OpenStream extension of OpenMP [4]: they are dedicated to loops with affine bounds only. Extensive analyses and graph and code transformations allow to model any kind of loops in PPNs [15] but then do not offer control of the degree of parallelism.…”

Polyhedral Dataflow Programming: A Case Study

“…Further optimizations are made, like hierarchic polyhedral scheduling for CRPs, or efficient implementation of communicating buffers for DPNs [29]. The Compaan compiler [30] transforms applications in the field of signal and image processing (thus inherently dataflow applications [31], written in Matlab) to PPNs, from which they can automatically derive an hardware description for FPGA platforms. Although there is a significant amount of research for deriving efficient control for PPNs with particular constraints coming from the hardware [32], all this process remains polyhedral.…”