Model Synthesis for Communication Traces of System Designs

Zheng, Hao; Ahmed, Rubel; Mukherjee, Parijat; Ketkar, Mahesh; Yang, Jin

doi:10.1109/iccd53106.2021.00082

Cited by 4 publications

(6 citation statements)

References 15 publications

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“…The multi-core gem5 simulation contains a high degree of interleaving. Besides a set of synthetic traces taken as a benchmark from work [11].…”

Section: Methodsmentioning

confidence: 99%

“…However, this tool performs poorly when there is a high degree of interleaving in the trace, a common scenario in SoC executions. Model synthesis technique AutoModel [11] extracts concise models from the highly interleaved traces. It can work with very long traces but produces too many models that often miss the true causality of the messages.The work BaySpec [12] produces LTL rules from Bayesian networks trained with software execution traces.…”

Section: Related Workmentioning

confidence: 99%

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Mining SoC Message Flows with Attention Model

Ahmed¹,

Bardia²,

Zheng³

2022

Preprint

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High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs. However, manual development and maintenance of such specifications are a daunting task. We propose a disruptive method that utilizes deep sequence modeling with the attention mechanism to infer accurate flow specifications from SoC communication traces. The proposed method can overcome the inherent complexity of SoC traces induced by the concurrent executions of SoC designs that existing mining tools often find extremely challenging. We conduct experiments on five highly concurrent traces and find that proposed approach outperforms several existing state-of-the-art trace mining tools.

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“…The multi-core gem5 simulation contains a high degree of interleaving. Besides a set of synthetic traces taken as a benchmark from work [11].…”

Section: Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Mining SoC Message Flows with Attention Model

Ahmed¹,

Bardia²,

Zheng³

2022

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

“…The states are often the unique events found in the trace and the transition are the relations between the states which are solved using SAT solvers. Prominent work in this category includes Trace2Model [3], model synthesis work [4], Mining Specifications [5] that propose tools and techniques to construct automatons from different types of traces. Model Synthesis from SoC IP communication traces described in [4] builds causality graphs using structural features of the messages.A SAT is used to solve the edges depending on the support information calculated from the trace.…”

Section: Classification Of Trace Minersmentioning

confidence: 99%

“…Prominent work in this category includes Trace2Model [3], model synthesis work [4], Mining Specifications [5] that propose tools and techniques to construct automatons from different types of traces. Model Synthesis from SoC IP communication traces described in [4] builds causality graphs using structural features of the messages.A SAT is used to solve the edges depending on the support information calculated from the trace. We consider Trace2Model from this category of tools to be studied in this paper.…”

Section: Classification Of Trace Minersmentioning

confidence: 99%

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Tools and Algorithms for SoC Communication Traces

Ahmed,

Zheng

2021

Preprint

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In this paper we study seven well-known trace analysis techniques both from the hardware and software domain, and discuss their performance on communication centric system-on-chip (SoC) traces. SoC traces are usually huge in size and concurrent in nature, therefore mining SoC traces poses additional challenges. We provide a hands on discussion of the selected tools/algorithms in terms of the input, output and analysis method they employ. Hardware traces also varies in nature when observed in different level, this work can help developers/academicians to pick up the right techniques for their works. We take advantage of a synthetic trace generator to find the interestingness of the mined outcomes for each tool as well as we work with a realistic GEM5 setup to find the performance of these tools on more realistic SoC traces. Comprehensive analysis of the tools performance and a benchmark trace dataset are also presented.

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Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions

Herget

Saadatmand

Bor

et al. 2022

2022 25th Euromicro Conference on Digital System Design (DSD)

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Industrial Cyber-Physical Systems (CPS) are complex heterogeneous and distributed computing systems, typically integrating and interconnecting a large number of subsystems and containing a substantial number of hardware and software components. Producers of these distributed Cyber-Physical Systems (dCPS) face serious challenges with respect to designing the next generations of these machines and require proper support in making (early) design decisions to avoid expensive and time consuming oversights. This calls for efficient and scalable systemlevel Design Space Exploration (DSE) methods for dCPS.In this position paper, we review the current state of the art in DSE, and argue that efficient and scalable DSE technology for dCPS is more or less non-existing and constitutes a largely unchartered research area. Moreover, we identify several research challenges that need to be addressed and discuss possible directions for targeting such DSE technology for dCPS.

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Model Synthesis for Communication Traces of System Designs

Cited by 4 publications

References 15 publications

Mining SoC Message Flows with Attention Model

Mining SoC Message Flows with Attention Model

Tools and Algorithms for SoC Communication Traces

Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions

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