2003
DOI: 10.1016/s0038-1101(03)00100-x
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Model for random telegraph signals in sub-micron MOSFETS

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Cited by 23 publications
(23 citation statements)
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“…The small operating drain bias (∼ 0.1V), relates the gate capacitive factor α g directly to an effective trap depth d t under the oxide surface. The relationship is linear in the oxide for a regular MOSFET with planar geometry, d t ≈ α g t ox , t ox denoting the thickness of the oxide layer [25,26]. Because of the cylindrical structure of the carbon nanotube FET the potential profile across the oxide varies logarithmically with distance from the center of the conductor.…”
mentioning
confidence: 99%
“…The small operating drain bias (∼ 0.1V), relates the gate capacitive factor α g directly to an effective trap depth d t under the oxide surface. The relationship is linear in the oxide for a regular MOSFET with planar geometry, d t ≈ α g t ox , t ox denoting the thickness of the oxide layer [25,26]. Because of the cylindrical structure of the carbon nanotube FET the potential profile across the oxide varies logarithmically with distance from the center of the conductor.…”
mentioning
confidence: 99%
“…3b − at 12%. RTS is well-known in submicron silicon MOSFETs [12,13] and also other similar devices. In those structures, however, RTS is primarily caused by deep-level traps located near an Si/SiO2 interface.…”
Section: I−v Characteristics In Forward and Reverse Bias At Low Tempementioning
confidence: 99%
“…Then, the trap position is computed along the channel from the source utilizing the reverse mode measurements: [2,5,7]. …”
Section: Measurement Setupmentioning
confidence: 99%