Model checking RAISE applicative specifications

Perna, Juan Ignacio; George, Chris

doi:10.1007/s00165-011-0217-0

Cited by 5 publications

(6 citation statements)

References 27 publications

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“…This method could also carry over to other, similar applications. The models are expressed in an extension to RSL: RSL-SAL [10]. Although stepwise development of state transition systems is well known from other languages, it is novel for RSL.…”

Section: Discussionmentioning

confidence: 99%

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Stepwise development and model checking of adistributed interlocking system using RAISE

Geisler

Haxthausen

2021

Form. Asp. Comput.

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Section: Discussionmentioning

confidence: 99%

“…For the system specification the method uses an extension of RSL, called RSL-SAL [10], which allows to specify systems by state transition system models. In contrast to this, the work in [8] used the RSL process algebra to specify the final model of the system.…”

Section: Contributionmentioning

confidence: 99%

Stepwise development and model checking of adistributed interlocking system using RAISE

Geisler

Haxthausen

2021

Form. Asp. Comput.

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“…In [15] the concept has been formalised in the RAISE Specification Language, RSL [27], and the RAISE theorem prover was used for verification. In [12] an extension of RSL, called RSL-SAL [23] was used for the formalisation, and the formal verification was performed using the SAL symbolic model checker. -Variant 1) US patent 8820685 B2 [22].…”

Section: Distributed Interlocking As Distributed Mutual Exclusionmentioning

confidence: 99%

Safety Interlocking as a Distributed Mutual Exclusion Problem

Fantechi

Haxthausen

2018

Formal Methods for Industrial Critical Systems

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“…Researches in (Dutertre and Sorea, 2004) (Brown and Pike, 2007) focused on specifying and analysing timed systems by exploiting the infinte bounded model checker of SAL. It has also been used to analyze models in other specification languages such as Z (Smith and Wildman, 2005) and RSL (Perna and George, 2007).…”

Section: Nusmvmentioning

confidence: 99%

Combining type-checking with model-checking for system verification

Ren

2016

2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)

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Type checking is widely used in mainstream programming languages to detect programming errors at compile time. Model checking is gaining popularity as an automated technique for systematically analyzing behaviors of systems. My research focuses on combining these two software verification techniques synergically into one platform for the creation of correct models for software designs. This thesis describes two modeling languages ATS/PML and ATS/Veri that inherit the advanced type system from an existing programming language ATS, in which both dependent types of Dependent ML style and linear types are supported. A detailed discussion is given for the usage of advanced types to detect modeling errors at the stage of model construction. Going further, various modeling primitives with well-designed types are introduced into my modeling languages to facilitate a synergic combination of type checking with model checking. The semantics of ATS/PML is designed to be directly rooted in a well-known modeling language PROMELA. Rules for translation from ATS/PML to PROMELA are designed and a compiler is developed accordingly so that the SPIN model checker can v be readily employed to perform checking on models constructed in ATS/PML. AT-S/Veri is designed to be a modeling language, which allows a programmer to construct models for real-world multi-threaded software applications in the same way as writing a functional program with support for synchronization, communication, and scheduling among threads. Semantics of ATS/Veri is formally defined for the development of corresponding model checkers and a compiler is built to translate ATS/Veri into CSP# and exploit the state-of-the-art verification platform PAT for model checking ATS/Veri models. The correctness of such a transformational approach is illustrated based on the semantics of ATS/Veri and CSP#. In summary, the primary contribution of this thesis lies in the creation of a family of modeling languages with highly expressive types for modeling concurrent software systems as well as the related platform supporting verification via model checking. As such, we can combine type checking and model checking synergically to ensure software correctness with high confidence. vi

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Model checking RAISE applicative specifications

Cited by 5 publications

References 27 publications

Stepwise development and model checking of adistributed interlocking system using RAISE

Stepwise development and model checking of adistributed interlocking system using RAISE

Safety Interlocking as a Distributed Mutual Exclusion Problem

Combining type-checking with model-checking for system verification

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