Model Checking Büchi Pushdown Systems

Abstract

Abstract. We develop an approach to model checking Linear Temporal Logic (LTL) properties of Büchi Pushdown Systems (BPDS). Such BPDS models are suitable for Hardware/Software (HW/SW) co-verification. Since a BPDS represents the asynchronous transitions between hardware and software, some transition orders are unnecessary to be explored in verification. We design an algorithm to reduce BPDS transition rules, so that these transition orders will not be explored by model checkers. Our reduction algorithm is applied at compile time; therefore, it is also suitable to runtime techniques such as co-simulation. As a proof of concept, we have implemented our approach in our co-verification tool, CoVer. CoVer not only verifies LTL properties on the BPDS models represented by Boolean programs, but also accepts assumptions in LTL formulae. The evaluation demonstrates that our reduction algorithm can reduce the verification cost by 80% in time usage and 35% in memory usage on average.

Formalizing hardware/software interface specifications

“…One way to introduce liveness constraints is via Linear Temporal Logic (LTL) assertions. In automata-theoretic approach, such LTL assertions can be represented as a Büchi automaton and then used to constrain the behavior of the target model during verification [20].…”

“…• During in-house testing, formal models can be utilized by validation techniques such as co-verification [6], [20] and co-simulation [1], [21]. There are three benefits: reduce the duplicate efforts in developing test harnesses; provides a uniform and systematic platform for validation; and improve the test coverage, since it is hard to manipulate real hardware devices to exhibit all possible interface behaviors (e.g., failures) in testing.…”