Model checking a SystemC/TLM design of the AMBA AHB protocol

Pockrandt, Marcel; Herber, Paula; Glesner, Sabine

doi:10.1109/estimedia.2011.6088527

Cited by 14 publications

(7 citation statements)

References 15 publications

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“…The notify method iterates through the ids beginning with the smallest and notifies the first unused list element it encounters. This drastically reduces the semantic state space of the resulting Uppaal model compared to our previously proposed formalization of the notify method as presented in [PHG11]. In addition, an overapproximation of the number of concurrent PEQ notifications has a significantly smaller impact on the semantic state space, as surplus list element automata are never used.…”

Section: Peq Notifymentioning

confidence: 95%

“…This includes the basic transformation rules for SystemC presented by Herber et al as well as our transformation rules for the TLM standard presented in [HPG11] and [PHG11]. We extended this implementation for our memory representation during the master thesis of Rolf Schröder [Sch13].…”

Section: Sc2uppaalmentioning

confidence: 99%

“…To overcome this problem, we developed an optimized representation of the time-ordered list, which exploits the semantics of Uppaal. This improved formalization was first presented in [PHG11]. Instead of creating a list in which all elements are stored, we create a single Uppaal template for each list element.…”

Section: Time-ordered Listmentioning

confidence: 99%

“…The resulting model can be used to verify important properties in TCTL with the Uppaal model checker. We have published the basic approach in [HPG11] and an optimized version in [PHG11].…”

Section: Main Contributionsmentioning

confidence: 99%

“…We first presented our formalization of the TLM 2.0 communication infrastructure in [HPG11] and an enhanced formalization featuring a strongly optimized version of the payload event queue in [PHG11].…”

Section: Formal Model Of Systemc/tlmmentioning

confidence: 99%

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Model Checking Memory-Related Properties of Hardware/Software Co-designs

Pockrandt

Herber

Klös

et al. 2013

IFIP Advances in Information and Communication Technology

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Hardware/software codesign enables the integrated development of hardware and software in a single design language. In combination with transaction level modeling, it can be used to efficiently model complex systems on different levels of abstraction. As such systems are often used in safety-critical applications, the correctness is crucial to prevent high financial losses or casualties. Especially memory-related errors can cause severe problems as they either result in deadlocks, runtime-errors or undefined system behavior. Although HW/SW codesign usually provides means for testing and simulation during the whole development process, these techniques are incomplete and can never ensure the absence of errors. In contrast, formal verification techniques like model checking can be used to guarantee the correctness of a design. Although there exist several approaches for the formal verification of HW/SW codesigns, memory-related constructs and operations are only insufficiently considered.In this thesis, we present an approach for model checking of memoryrelated properties on digital HW/SW systems. To this end, we focus on the system level description language SystemC, the de facto standard for HW/SW codesign. To support transaction level modeling, we additionally take the widely used SystemC transaction level modeling standard (TLM) into account. The main idea of our approach is to provide a formal semantics for the most relevant parts of the TLM standard and a formal memory model, which captures all relevant memory-related constructs and operations. We combine these with an already existing formalization of the basic SystemC constructs and provide transformation rules to enable the fully automatic transformation of SystemC/TLM designs into semantically equivalent Uppaal timed automata models. On the resulting model, we use the Uppaal model checker to verify important properties, including memory-related properties, timing, liveness and safety properties. To ease this verification, we automatically generate a set of verification properties, which can be used to ensure the absence of many common errors in a given design. This includes memory-related errors like null pointer accesses and array out of bounds accesses on a given design as well as the absence of assertion violations.If a property is violated, the Uppaal model checker generates a counterexample. As our formal semantics for SystemC/TLM is structure-preserving, this counterexample can easily be transferred back to the SystemC/TLM code manually and thereby allows for the localization of detected errors. To enhance the applicability of our approach for complex designs, we provide a set of optimization techniques. These are used to reduce the semantic state space and, thus, yield a better verification performance.We have implemented our transformation and our optimization techniques in a toolchain, which can be applied to SystemC/TLM designs fully automatically. We demonstrate both, the verification performance and the errordetection capabilities of ...

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Section: Peq Notifymentioning

confidence: 95%

Section: Sc2uppaalmentioning

confidence: 99%

Section: Time-ordered Listmentioning

confidence: 99%

“…The resulting model can be used to verify important properties in TCTL with the Uppaal model checker. We have published the basic approach in [HPG11] and an optimized version in [PHG11].…”

Section: Main Contributionsmentioning

confidence: 99%

Section: Formal Model Of Systemc/tlmmentioning

confidence: 99%

See 3 more Smart Citations