2019 22nd Euromicro Conference on Digital System Design (DSD) 2019
DOI: 10.1109/dsd.2019.00090
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Model-Based Processor-in-the-Loop Framework for Composable Multi-core Platforms

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“…In this way, the designer can upload the executable on the corresponding VEPs of the processor tile. Authors in [13] proposed the framework which explains the different configurations for PIL targetting multi-processor platforms. In this paper, we demonstrate PIL simulation for the vision-based control on CompSOC.…”
Section: E Pil Simulationmentioning
confidence: 99%
“…In this way, the designer can upload the executable on the corresponding VEPs of the processor tile. Authors in [13] proposed the framework which explains the different configurations for PIL targetting multi-processor platforms. In this paper, we demonstrate PIL simulation for the vision-based control on CompSOC.…”
Section: E Pil Simulationmentioning
confidence: 99%