Mobility and quasi-ballistic charge carrier transport in graphene field-effect transistors

Abstract

The optimization of graphene field-effect transistors (GFETs) for high-frequency applications requires further understanding of the physical mechanisms concerning charge carrier transport at short channel lengths. Here, we study the charge carrier transport in GFETs with gate lengths ranging from 2 [Formula: see text]m down to 0.2 [Formula: see text]m by applying a quasi-ballistic transport model. It is found that the carrier mobility, evaluated via the drain–source resistance model, including the geometrical magnetoresistance effect, is more than halved with decreasing the gate length in the studied range. This decrease in mobility is explained by the impact of ballistic charge carrier transport. The analysis allows for evaluation of the characteristic length, a parameter of the order of the mean-free path, which is found to be in the range of 359–374 nm. The mobility term associated with scattering mechanisms is found to be up to 4456 cm[Formula: see text]/Vs. Transmission formalism treating the electrons as purely classical particles allows for the estimation of the probability of charge carrier transport without scattering events. It is shown that at the gate length of 2 [Formula: see text]m, approximately 20% of the charge carriers are moving without scattering, while at the gate length of 0.2 [Formula: see text]m, this number increases to above 60%.

A Scalable Compact Model for the Static Drain Current of Graphene FETs

“…5a). The ~1/L relation of μ(p)n and ~L of Δ for shorter L for all examined technologies are confirmed [26] (cf. Fig.…”

“…In GFETs, peak gm has been recorded to degrade due to a μ reduction at short channels [17]. Such behavior can be induced either by an e-beam damage during metal-contact fabrication process [24], by contact-metal doping effects [27] and/or by a strong quasi-ballistic transport which becomes more critical as L decreases [23]- [26]. Besides, long-range Coulomb scattering effects can also decrease μ in GFETs [26], similarly to CMOS.…”

“…In this work, such critical scaling effects are investigated, for an industry-based GFET technology (Graphenea PF1) [15], as well as for different published GFET technologies, mainly developed in research labs [16]- [20]. Geometrical variations have been earlier experimentally studied for Dirac voltage VDirac (VTH equivalent in GFETs) in [17], [18], for Rd(s) in [20]- [23], for μ in [17], [23]- [27] and for impuritiesrelated residual charge nres in [26], however, such [23], [25], [28]. For the extraction of the basic parameters of the model (VDirac-related flat-band voltage VG0, Rd(s), μ, intrinsic mobility degradation θint [29] and nres-related parameter Δ) [5] several methodologies have been proposed [29], [30] where the one presented in [29], is applied here.…”