MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems

Zhu, Zhenhua; Sun, Hanbo; Qiu, Kaizhong; Xia, Lixue; Krishnan, Gokul; Dai, Guohao; Niu, Dimin; Chen, Xiaoming; Hu, Xiaobo Sharon; Cao, Yu; Xie, Yuan; Wang, Yu; Yang, Huazhong

doi:10.1145/3386263.3407647

Cited by 51 publications

(18 citation statements)

References 6 publications

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“…We follow the MNSIM [13] architecture. A PE contains G crossbar groups and each such group consists of a single crossbar for mapping scheme 1 or a crossbar pair for mapping scheme 2.…”

Section: Implementing the Protection Methodsmentioning

confidence: 99%

Enhancing Security of Memristor Computing System Through Secure Weight Mapping

Zou,

Zhou,

Cui

et al. 2022

Preprint

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Emerging memristor computing systems have demonstrated great promise in improving the energy efficiency of neural network (NN) algorithms. The NN weights stored in memristor crossbars, however, may face potential theft attacks due to the nonvolatility of the memristor devices. In this paper, we propose to protect the NN weights by mapping selected columns of them in the form of 1's complements and leaving the other columns in their original form, preventing the adversary from knowing the exact representation of each weight. The results show that compared with prior work, our method achieves effectiveness comparable to the best of them and reduces the hardware overhead by more than 18X.

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“…We follow the MNSIM [13] architecture. A PE contains G crossbar groups and each such group consists of a single crossbar for mapping scheme 1 or a crossbar pair for mapping scheme 2.…”

Section: Implementing the Protection Methodsmentioning

confidence: 99%

Enhancing Security of Memristor Computing System Through Secure Weight Mapping

Zou,

Zhou,

Cui

et al. 2022

Preprint

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“…Each tile consists of several crossbar sub-arrays which perform the IMC operation. Existing implementations of DNN accelerators use both P2P-based [16,33] and NoC-based [14,30,36] interconnect for on-chip communication. To better understand the performance of different interconnect architectures, we plot the average interconnect latency for a P2P network with 64 nodes, NoC-tree with 64 nodes, and an 8×8 NoC-mesh with X-Y routing as shown in Figure 5.…”

Section: Interconnect Networkmentioning

confidence: 99%

Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks

Krishnan

Mandal

Chakrabarti

et al. 2021

J. Emerg. Technol. Comput. Syst.

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With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions—one with ever-increasing connection density for better accuracy and the other with more compact sizing for energy efficiency. The increase in connection density increases on-chip data movement, which makes efficient on-chip communication a critical function of the DNN accelerator. The contribution of this work is threefold. First, we illustrate that the point-to-point (P2P)-based interconnect is incapable of handling a high volume of on-chip data movement for DNNs. Second, we evaluate P2P and network-on-chip (NoC) interconnect (with a regular topology such as a mesh) for SRAM- and ReRAM-based in-memory computing (IMC) architectures for a range of DNNs. This analysis shows the necessity for the optimal interconnect choice for an IMC DNN accelerator. Finally, we perform an experimental evaluation for different DNNs to empirically obtain the performance of the IMC architecture with both NoC-tree and NoC-mesh. We conclude that, at the tile level, NoC-tree is appropriate for compact DNNs employed at the edge, and NoC-mesh is necessary to accelerate DNNs with high connection density. Furthermore, we propose a technique to determine the optimal choice of interconnect for any given DNN. In this technique, we use analytical models of NoC to evaluate end-to-end communication latency of any given DNN. We demonstrate that the interconnect optimization in the IMC architecture results in up to 6 × improvement in energy-delay-area product for VGG-19 inference compared to the state-of-the-art ReRAM-based IMC architectures.

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“…Benchmarking tools enable a fast design space exploration. Prior work have proposed a number of benchmarking tools for IMC-based architectures [2,6,15,21,29,32,44] and conventional von-Neumann architectures [4,31,33]. Authors in [29] provide a DNN inference benchmarking tool for different device technologies.…”

Section: Benchmarking Toolsmentioning

confidence: 99%

“…The architecture utilizes an array of IMC crossbars and peripheral circuits connected by point-to-point (P2P) interconnect for on-chip data movement. Recently, authors in [44] proposed a behavioral performance benchmarking tool for IMC architectures. They utilize individual models for each component in the IMC architecture to perform the estimation.…”

Section: Benchmarking Toolsmentioning

confidence: 99%

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SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks

Krishnan,

Mandal,

Pannala

et al. 2021

Preprint

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In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes. 2.5D integration or chiplet-based architectures interconnect multiple small chips (i.e., chiplets) to form a large computing system, presenting a feasible solution beyond a monolithic IMC architecture to accelerate large deep learning models. This paper presents a new benchmarking simulator, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore the potential of such a paradigm shift in IMC architecture design. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to realize an end-to-end system. SIAM is scalable in its support of a wide range of deep neural networks (DNNs), customizable to various network structures and configurations, and capable of efficient design space exploration. We demonstrate the flexibility, scalability, and simulation speed of SIAM by benchmarking different state-of-the-art DNNs with CIFAR-10, CIFAR-100, and ImageNet datasets. We further calibrate the simulation results with a published silicon result, SIMBA. The chiplet-based IMC architecture obtained through SIAM shows 130× and 72× improvement in energy-efficiency for ResNet-50 on the ImageNet dataset compared to Nvidia V100 and T4 GPUs. CCS Concepts: • Hardware → Analysis and Design of Emerging Devices and Systems; On-chip Resource Management; Emerging Architectures; Interconnect; System-on-a-chip.

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MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems

Cited by 51 publications

References 6 publications

Enhancing Security of Memristor Computing System Through Secure Weight Mapping

Enhancing Security of Memristor Computing System Through Secure Weight Mapping

Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks

SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks

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