MMSE equalization of multi-Gb/s chip-to-chip interconnects with M-PAM signaling affected by manufacturing tolerances

Bailleul, Jelle; Jacobs, Lennert; Manfredi, Paolo; Ginste, Dries Vande; Moeneclaey, Marc

doi:10.1109/scvt.2016.7797658

Cited by 2 publications

(1 citation statement)

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“…where the PRF is fixed but the FBF is adjustable. While strategy (i) constitutes the standard approach from literature when dealing with channel variability, the strategies (ii) and (iii) have, to the best of our knowledge, been investigated for the first time in [13]. The present paper extends the results from [13] in the following ways: a more comprehensive derivation of the optimum taps of the PRF and FBF is presented, the tap spacing of the PRF is not restricted to the symbol interval, the sampling delay at the RX is optimized, and the performance is evaluated for two levels of channel variability.…”

Section: Introductionmentioning

confidence: 99%

Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

Bailleul

Jacobs

Manfredi

et al. 2017

Computers & Electrical Engineering

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Electrical chip-to-chip interconnects suffer from considerable intersymbol interference at multi-Gb/s data rates, due to the frequency-dependent attenuation. Hence, reliable communication at high data rates requires equalization, to compensate for the channel response. As these interconnects are prone to manufacturing tolerances, the equalizer must be adjusted to each specific channel realization to perform optimally. We adopt a reduced-complexity equalization scheme where (part of) the equalizer is fixed, by involving the channel statistics into the equalizer derivation. For a 10 cm on-board microstrip interconnect with a 10% tolerance on its parameters, we point out that 2-PAM transmission using a fixed prefilter and an adjustable feedback filter, both with few taps, yields only a moderate bit error rate degradation, compared to the all-adjustable equalizer; at a bit error rate of 10 −12 , these degradations are about 1.1 dB and 3 dB, when operating at 20 Gb/s and 80 Gb/s, respectively.

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Section: Introductionmentioning

confidence: 99%

Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

Bailleul

Jacobs

Manfredi

et al. 2017

Computers & Electrical Engineering

Self Cite

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MIMO Equalization for Multi-Gbit/s Access Nodes Affected by Manufacturing Tolerances

Jacobs

Bailleul

Manfredi

et al. 2017

GLOBECOM 2017 - 2017 IEEE Global Communications Conference

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Abstract-While the requirements for delivering high throughputs increase exponentially with every generation of access node hardware, the device cost is of primary concern. As a result, multiple-input multipleoutput (MIMO) equalization, which has been shown to facilitate multi-Gbit/s communication over low-cost parallel electrical interconnects, is emerging as an attractive high-speed interconnect solution for next-generation access nodes. Because of the high operating frequencies, however, the transfer functions of the on-and off-chip interconnects become highly susceptible to manufacturing tolerances (MTs); hence, the equalization filters must be adjusted to the specific channel realization to achieve optimal performance, which involves a high implementation and computational complexity. Considering that the MTs are usually limited, we propose a robust lowcomplexity transceiver consisting of a fixed MIMO linear pre-equalizer (which avoids the need for feeding back the channel state information to the transmitter), with either a fixed or adjustable MIMO decision-feedback equalizer (DFE). For a specific chip-to-chip interconnect operating at 75 Gbit/s per line and a 26 dB signal-to-noise ratio, we show that the resulting bit error rate does not exceed 10 −12 for MTs up to 10.5% (fixed DFE) and 17.7% (adjustable DFE) of the nominal line width.

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MMSE equalization of multi-Gb/s chip-to-chip interconnects with M-PAM signaling affected by manufacturing tolerances

Cited by 2 publications

References 6 publications

Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

MIMO Equalization for Multi-Gbit/s Access Nodes Affected by Manufacturing Tolerances

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