MLXR: multi-layer obstacle-avoiding X-architecture Steiner tree construction for VLSI routing

Huang, Xing; Guo, Wenzhong; Liu, Genggeng; Chen, Guolong

doi:10.1007/s11432-015-0850-4

Cited by 20 publications

(5 citation statements)

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“…In recent years, more and more researches [55]- [58], [60], [61], [70], [84], [85] have been conducted on X-architecture SMT construction. However, most of the SI algorithms are used to solve the RSMT problem.…”

Section: A Multi-layer Routing Based On X-architecturementioning

confidence: 99%

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

et al. 2020

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Routing is a complex and critical stage in the physical design of Very Large Scale Integration (VLSI), minimizing interconnect length and delay to optimize overall chip performance. With the rapid development of modern technology, VLSI routing faces enormous challenges such as large delay, high congestion, and high-power consumption. As a rising optimization method, Swarm Intelligence (SI) inspired from collective intelligence behaviors through cooperation or interaction with the environment provides effectiveness and robustness for solving NP-hard problems. Many researchers have consequently used SI techniques to solve routing-related problems in VLSI. This paper reviews the application of several SI techniques to the VLSI routing filed. Firstly, five commonly used SI techniques and related models, and three classic routing problems are described: Steiner tree construction, global routing and detailed routing. Then an overview of the current state of this field is given according to the above categories, and the survey offers informative discussions from five aspects: 1) Steiner minimum tree construction; 2) wirelength-driven routing; 3) obstacle-avoiding routing; 4) timing-driven routing; 5) power-driven routing. Finally, under three new technology models: X-architecture, multiple dynamic supply voltage and via-pillar, the future development trends are pointed as follows: 1) suggesting suitable SI techniques to specific routing problems for advanced technology models; 2) exploring new and available SI techniques that have not yet been applied to VLSI routing.

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Section: A Multi-layer Routing Based On X-architecturementioning

confidence: 99%

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

et al. 2020

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“…An algorithm called MLXR was proposed by Huang et al [69], which is based on a lookup table and builds a 3D obstacle-free minimum tree as the basic architecture. An effective projection-based obstacle avoidance strategy is utilized to accurately capture the appropriate Steiner point position in a multi-layer environment.…”

Section: B Oasmtmentioning

confidence: 99%

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

et al. 2020

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Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration (VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall chip performance. Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design. In a GR process, a Steiner Minimum Tree (SMT) algorithm can be invoked millions of times, which means that SMT algorithm has great significance for the final quality of GR. Some of the research works are surveyed in this paper to understand GR and SMT problems and to learn the available solutions. Firstly, we systematically dissect three types of subproblems in Steiner tree construction and three types of GR methods. Then, we investigate the recent progress under two new technology models. Finally, the survey concludes with a summary of possible future research directions.

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“…This is because in the octilinear condition, the time complexity and memory usage of the traditional maze routing algorithms grow prohibitively huge as the routing area becomes larger, and this drawback make the maze-routing based approaches less popular for modern applications. For the obstacle-avoiding octilinear MST (OAOMST) problem, Huang et al [49] proposed a Particle Swarm Optimization-based (PSO) single-layer OAOMST approach 2015, and further improved its performance with the concept of DT [50] and applied it to the X-Architecture [51].…”

Section: Steiner Problem and Current Related Work A The Steinermentioning

confidence: 99%

An Efficient Rectilinear and Octilinear Steiner Minimal Tree Algorithm for Multidimensional Environments

2020

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The rectilinear/octilinear Steiner problem is the problem of connecting a set of terminals Z using orthogonal and diagonal edges with minimum length. This problem has many applications, such as the EDA, VLSI circuit design, fault-tolerant routing in mesh-based broadcast, and Printed Circuit Board (PCB). This paper proposes an obstacle-avoiding 4/8/10/26-directional heuristic algorithm for this problem based on the Areibi's concept, Higher Geometry Maze Routing, and Sollin's minimal spanning tree algorithm. The major contributions of this paper are (1) our work is the first report for the octilinear SMTs in the multidimensional environments, (2) we provide an optimal point-to-point routing without any refinement, and (3) the proposed algorithm has higher adaptability to deal with any irregular environment, and can be extended to the λ-geometry without any extra work, where λ = 2, 4, 8 and ∞ corresponding to rectilinear, 45 • , 22.5 • and Euclidean geometries respectively. INDEX TERMS Higher geometry maze routing, octilinear, rectilinear, Steiner tree.

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MLXR: multi-layer obstacle-avoiding X-architecture Steiner tree construction for VLSI routing

Cited by 20 publications

References 5 publications

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

An Efficient Rectilinear and Octilinear Steiner Minimal Tree Algorithm for Multidimensional Environments

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