Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
DOI: 10.1109/iscas.2003.1205966
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Mixer topology selection for a 1.8 - 2.5 GHz multi-standard front-end in 0.18 μm CMOS

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Cited by 19 publications
(12 citation statements)
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“…6). Simulated performance of the proposed mixer and the reported mixers [5][6][7][8][9][10] are given in Table 1. Among them, refs.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…6). Simulated performance of the proposed mixer and the reported mixers [5][6][7][8][9][10] are given in Table 1. Among them, refs.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…The minimal IIP is 48 dBm and its average value is 52 dBm. The figure of merit (FOM) is set for fair comparison [17], [34].…”
Section: A Low-voltage Ac-coupling Folded-switch Dbmmentioning
confidence: 99%
“…These designs achieve low-power and low-voltage performance despite their relative low CG and IIP due to the limited voltage swing across the IF load [7]- [16]. Therefore, a folded-switch topology has been proposed to reduce the supply voltage and power consumption while keeps high CG, IIP and port-to-port isolations, [17]- [23]. However, few studies discussed these important features related to low-voltage operation.…”
Section: Introductionmentioning
confidence: 99%
“…6). Simulated performance of the proposed mixer and the reported mixers [5][6][7][8][9][10] are given in Table 1. The performance of the proposed mixer can also be expressed by a figure of merit (FOM).…”
Section: Introductionmentioning
confidence: 99%