Mixed-width instruction sets

Abstract

A pplications written for the embedded domain must perform under the constraints of limited memory and limited energy. While these constraints have always existed, current trends, such as mobile computing and ubiquitous computing, bring more and more complex applications to the embedded domain, making performance, or speed of execution, an important factor as well. For instance, we are now able to run resource-intensive gaming and multimedia applications on handheld devices. Techniques that reduce the memory and energy consumption of programs have in general done so at the cost of performance. Simultaneously achieving small code size, low energy consumption, and high performance is a challenging task.Processors, such as the ARM and MIPS family of embedded cores, support more than one instruction set to meet these constraints. In addition to the 32-bit instruction set, they support a 16-bit instruction set. As we will explain, by using 16-bit code one can achieve code size and energy reduction at the cost of performance.Until recently, the choice between 32-bit and 16-bit code had to be made by the programmer, and is highly undesirable. In this article, we show how this task can be automated and how one can achieve the code-size and energy-saving properties of 16-bit code while simultaneously achieving performance comparable to 32-bit code. We focus on the encoding of a program's computations. This is in contrast to the previous articles in this special section, which primarily focus on the elimination of superfluous computations from a program. The techniques described here are in the context of the ARM family of processors, which are frequently used in the embedded computing realm. They are used as general-purpose embedded processors, found, for example, on multimedia-enabled PDAs, as well as in specialized embedded applications, such as embedded control.ARM processors have a simple energy-efficient architecture. The StrongARM [8],Encoding a program's computations to reduce memory and power consumption without sacrificing performance.

Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions

“…It is important to note that although we are using feedback to guide instruction selection in our compact code generation methodology, this feedback information is generated statically within the compiler and unlike [10,11,12] …”

“…The reason why most of the prior work in this field [9,10,11,12,16] has reported performance losses or, at best, the same level of performance for mixed-mode code is that the mode switching overhead associated with the Thumb, Thumb-2 and MIPS16e ISAs exceeds the performance gains from a reduced number of instruction cache misses. Due to the ability to freely interleave compact and standard instructions without mode switch the ARCompact ISA does not suffer this penalty.…”

“…Compact instruction sets are supported by a number of commercial embedded processors and code size aware compilation techniques targeting these short instruction formats have found significant interest in the scientific community [9,10,11,12,16]. All of these papers address mixed mode code generation where there is an overhead associated with switching between compact and standard instruction sets.…”

“…Feedback information is used in [10,11] for the selection of ARM and Thumb instructions. Frequently executed functions are identified via profiling before a heuristic based on expected performance and relative code size is used to choose between 32-bit ARM and 16-bit Thumb instructions.…”

“…Sig-nificant care needs to be taken as performance degradation by up to 98% as a result of an overly aggressive use of compact instructions has been reported in e.g. [11].…”