Mixed SW/SystemC SoC Emulation Framework

Montón, Màrius; Portero, Antoni; Moreno, M.; Martínez, Borja; Carrabina, Jordi

doi:10.1109/isie.2007.4374971

Cited by 51 publications

(29 citation statements)

References 4 publications

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“…SystemC also provides support for integrating different Instruction Set Simulators (ISS) in a unified system simulation framework, as it is able to plug an independent ISS into the entire simulation framework (as a new system module), where all system modules can be activated and synchronized through a common reference clock. Furthermore, SystemC based simulators (such as [123][124][125][126][127]) can benefit from advantages of C++ language as a hardware description language while bridging the gap between hardware and software description languages [123]. In fact, one of the most important advantages of C/C++ based description languages such as SystemC (or SpecC [128], a similar alternative) is their capability to concurrently specify both hardware and software components in the design (i.e.…”

Section: Systemcmentioning

confidence: 99%

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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This is the accepted version of the paper.This version of the publication may differ from the final published version. Permanent repository link AbstractThe architecture design of peta-scale computing systems is complex and presents lots of difficulties to designs, as current tools lack support for relevant features of future scenarios. Novel systems must be designed with great care and tools, such as manycore architecture simulators, must be adapted accordingly. However, current simulation tools are very slow, often specific-purposeoriented, suffer from various issues and are rarely able to simulate thousands of cores. The emergence of peta-scale systems and the upcoming manycore era brings nevertheless new challenges to computing systems and architectures, adding further difficulties and requirements on the development of the corresponding simulators. Furthermore, the design of architecture simulators for manycore systems involve methods and techniques from various interdisciplinary research areas, which in turn brings more challenges in different aspects. As system complexity grows, the growth of the simulation capacity is being outpaced (reaching the so called simulation wall). In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques. The aim of this work is to highlight how current approaches can best deal with the identified problems, smoothing the challenges of research in future peta-scale systems.

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Section: Systemcmentioning

confidence: 99%

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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“…The core of the simulation platforms is a set of libraries to connect QEMU and SystemC so that users can easily devlop their own simulators. Examples of such simulation platforms include QBox [9,10], TLMu [11], and Rabbits [12,13]. Some of them support simulation of multi-core architectures, but to the best of our knowledge, they are not used for simulation of NoCs with more than 100 cores.…”

Section: Related Workmentioning

confidence: 99%

Naxim: A Fast and Retargetable Network-on-Chip Simulator with QEMU and SystemC

Nakajima

Kurebayashi

Fukutsuka

et al. 2013

IJNC

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Systems-on-Chip (SoC) architectures have been shifting from single-core to multi-core solutions, and they are at present evolving towards many-core ones. Network-on-Chip (NoC) is considered as a promising interconnection scheme for many-core SoCs since it offers better scalability than traditional bus-based interconnection. In this work, we have developed a fast simulator of NoC architectures using QEMU and SystemC. QEMU is an open-source CPU emulator which is widely used in many simulation platforms such as Android Emulator. In the proposed simulator, each CPU core is emulated by a QEMU, and the network part including NoC routers is modeled with SystemC. The SystemC simulator and QEMUs are connected by TCP sockets on a host computer. Our simulator is fast because QEMUs run in parallel on a multi-core host computer or even multiple host computers. Also, our simulator is highly retargetable because QEMU provides a variety of CPU models and we use QEMU as is. In our experiments, our simulator successfully simulates a 108-core NoC in a practical time. We have also confirmed the scalability and retargetability of our NoC simulator.

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“…Unfortunately these emulation tools are not able to tackle efficiently the complexity and heterogeneity of state-of-the-art SoCs [12,20]. Some work [23,14,30,29] has been focused on enhancing QEMU with the capability of a more accurate hardware simulation infrastructure by interfacing QEMU with SystemC[11]. However, QEMU performance is also strongly affected by the poor performance of the SystemC simulation when it is targeted for manycore simulation.…”

Section: Related Workmentioning

confidence: 99%

Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting

Raghav

Marongiu

Pinto

et al. 2012

Proceedings of the 5th Annual Workshop on General Purpose Processing With Graphics Processing Units

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Modern system-on-chips are evolving towards complex and heterogeneous platforms with general purpose processors coupled with massively parallel manycore accelerator fabrics (e.g. embedded GPUs). Platform developers are looking for efficient full-system simulators capable of simulating complex applications, middleware and operating systems on these heterogeneous targets. Unfortunately current virtual platforms are not able to tackle the complexity and heterogeneity of state-of-the-art SoCs. Software emulators, such as the open-source QEMU project, cope quite well in terms of simulation speed and functional accuracy with homogeneous coarse-grained multi-cores. The main contribution of this paper is the introduction of a novel virtual prototyping technique which exploits the heterogeneous accelerators available in commodity PCs to tackle the heterogeneity challenge in full-SoC system simulation. In a nutshell, our approach makes it possible to partition simulation between the host CPU and GPU. More specifically, QEMU runs on the host CPU and the simulation of manycore accelerators is offloaded, through semi-hosting, to the host GPU. Our experimental results confirm the flexibility and efficiency of our enhanced QEMU environment.

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Mixed SW/SystemC SoC Emulation Framework

Cited by 51 publications

References 4 publications

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Naxim: A Fast and Retargetable Network-on-Chip Simulator with QEMU and SystemC

Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting

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