Mixed-mode ATPG under input constraints

Glover, Clive

doi:10.1109/test.1990.114012

Cited by 11 publications

(6 citation statements)

References 9 publications

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“…In the next TCLK[l] these addresses are received and decoded by the row decoders to select one row line on the cache data array. In TCLK [3] data is read from the cache array and then placed in the CLHR register. In the next TCLK[4] the data is moved to a shadow register.…”

Section: Cache Data and Tag Ad-hoc Modementioning

confidence: 99%

“…In the next TCLK[4] the data is moved to a shadow register. Following the reading of the specified cache data, the data is transferred to the pins at the TCLK[2]/TCLK [3] transition. The Dcache data array is tested in a similar manner.…”

Section: Cache Data and Tag Ad-hoc Modementioning

confidence: 99%

“…Then, the first write address given after the read sequence will write the data that was preloaded in the line read buffer. and is read out during TCLK[2]/TCLK [3]. The instruction tag array is tested in a similar manner.…”

Section: Cache Data and Tag Ad-hoc Modementioning

confidence: 99%

“…The R1 W line is set to indicate write. The line read buffer is loaded in TCLK[3] with the LW data and the snoop address buffer is loaded in TCLK[4] with the address. All four LWs in the read buffer are loaded with the same data, which constrains the data array test to a single LW in a line at a time.…”

mentioning

confidence: 99%

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Testability features of the 68040

Gallup

Ledbetter

McGarity

et al.

Proceedings. International Test Conference 1990

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This paper describes the design and implementation of onchip test functions on the 68040 microprocessor. The discussion includes an introduction to the 68040 along with the testability goals and objectives that were set in the beginning of the design. Further discussions detail the different design for testability (DFT) techniques used to control and observe the behavior of the 68040 subsystems. Topics covered include the global test architecture, special test modes for the intemal RAM arrays, the scan circuitry used for structural testing of random logic, and the IEEE 1149.

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Section: Cache Data and Tag Ad-hoc Modementioning

confidence: 99%

Section: Cache Data and Tag Ad-hoc Modementioning

confidence: 99%

Section: Cache Data and Tag Ad-hoc Modementioning

confidence: 99%

mentioning

confidence: 99%

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Testability features of the 68040

Gallup

Ledbetter

McGarity

et al.

Proceedings. International Test Conference 1990

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“…Since the scan rule violations usually constrain the possible set of primary input logic values during test mode, the idealized combinational lest pattern generation tools may not be directly used for the logic circuits with design constraints [Glover90]. Furthermore, in testing for a large logic circuit, the entire logic circuit is usually partitioned into several logic blocks according to their functionalities.…”

Section: Introductionmentioning

confidence: 99%

A pragmatic test pattern generation system for scan-designed circuits with logic value constraints

Park

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

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In testing for practical logic circuits, there may exist logic value constraints on some part of logic circuits owing to various requirements on design and test. n i e inefficiency in handling the logic value constraints during the line justification stage of test generation may result in low fault coverage as well as excessive computer time with numerous fruitless searches. This paper presents a logic value system called fuhoo logic vtrfue to represent the logic value constraints and to identify additional logic value constraints using a taboo logic calculus. Also, a test pattern generation algorithm will be discussed to show how the taboo logic system can be incorporated into existing test generation algorithms. Finally, experimental results demonstrate the efficiency of the taboo logic values.

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