Mixed Full Adder topologies for high-performance low-power arithmetic circuits

Alioto, Massimo; Cataldo, G. Di; Palumbo, G.

doi:10.1016/j.mejo.2006.09.001

Cited by 63 publications

(13 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…10, respectively. Vasefi [16] Tung [17] Alioto [18] Abid [19] Proposed It should be mentioned again that as discussed before, the carry propagation delay is determinant in overall delay and so delay comparisons have been made among carry propagation delays. It's conspicuous that except the proposed circuit, there is only one work with less than 100 ps delay and in comparison to that work we had almost 9 percent of improvement.…”

Section: Discussionmentioning

confidence: 99%

“…By the way, to have a better view of different aspects of proposed circuit and other works, numerical results, comparisons and improvements are inserted in Table IV. Vasefi [16] Tung [17] Alioto [18] Abid [19] Proposed It can be easily seen that in all cases new proposed hybrid analog-digital circuit could improve predecessor full adders in delay, power consumption and PDP criteria. The only exception is the power consumption respecting to that one proposed in [16], in which the power consumption of proposed circuit was 33.7% worse than [16] while the delay has been 544% improved.…”

Section: Delay Comparisionmentioning

confidence: 97%

See 1 more Smart Citation

A new high speed, low power adder; using hybrid analog-digital circuits

TaheriNejad

Abrishamifar

2009

2009 European Conference on Circuit Theory and Design

View full text Add to dashboard Cite

In this paper a new high speed and low power adder is presented. The circuit uses a hybrid concept of analog and digital circuit design to propagate the carry and so achieve a Full Adder with 78 ps delay and 7.26 μw of power consumption. SPICE Simulations performed on the 0.18 μm TSMC Technology demonstrates the average improvement of 159%, 184% and 516%, respectively for Delay, Power Consumption and PDP.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Delay Comparisionmentioning

confidence: 97%

A new high speed, low power adder; using hybrid analog-digital circuits

TaheriNejad

Abrishamifar

2009

2009 European Conference on Circuit Theory and Design

View full text Add to dashboard Cite

show abstract

“…2) were made relatively larger and smaller, respectively. The layout area (excluding buffer) in the present design is higher (6.55%) than that of TFA which is also comprised 16 transistors [21]. When compared with the best design in terms of area (10 T) [24], the proposed design of the adder (excluding buffer) consumed 44.5% more area.…”

Section: B Calculation Of Propagation Delaymentioning

confidence: 92%

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Bhattacharyya

Kundu

Ghosh

et al. 2015

IEEE Trans. VLSI Syst.

231

View full text Add to dashboard Cite

In this paper, a hybrid 1-bit full adder design employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 µW) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 µW and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79-µW (53.36-µW) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.Index Terms-Carry propagation adder, high speed, hybrid design, low power.

show abstract

“…So, enhancing the performance of the full adder cell is essential to enhance the overall system/architecture performance. Many full adder designs employing different logic styles and technologies have been reported in the literature [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]. Some designs are based on single logic style and some other designs use multiple logic styles (hybrid designs).…”

Section: Introductionmentioning

confidence: 99%

Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems

Sanapala

Sakthivel

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

In recent years, ultra-low-voltage (ULV) operation is gaining more importance for achieving minimum energy consumption. Full adder is the basic computational arithmetic block in many of the computing and signal/image processing applications. Here, a new hybrid 1-bit full adder circuit which employs both Gate Diffusion Input (GDI) logic and multi-threshold voltage (MVT) transistor logic is reported. The main objective of the proposed MVT-GDI-based hybrid full adder design is to provide minimum energy consumption with less area. The proposed hybrid design is simulated using standard 45 nm CMOS process technology at an ULV of 0.2 V. The post-layout simulation results have shown that the proposed design achieved significant improvements in comparison with the other reported designs by achieving >57%, 92% savings in the Energy and EDP, respectively, with only 14 transistors. Monte-Carlo simulations have also been performed and is found that the proposed design methodology yields full functionality and robustness against local and global process variations. Normalised energy metrics to 32 and 22 nm technologies shows that the proposed design achieves >57% energy savings in prior to the recent works.

show abstract

Mixed Full Adder topologies for high-performance low-power arithmetic circuits

Cited by 63 publications

References 19 publications

A new high speed, low power adder; using hybrid analog-digital circuits

A new high speed, low power adder; using hybrid analog-digital circuits

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems

Contact Info

Product

Resources

About