Mixed Design of SPAD Array Based TOF for Depth Camera and Unmanned Vehicle Applications

Shi, Weiwei; Pan, An

doi:10.1109/smacd.2018.8434860

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…Since the root-mean-square error varies for different time intervals, the measured interval should be at least greater than one cycle. After testing 2 10 for each interval to be measured, some results approximate the synthetic Gaussian distribution, but are not exact. As shown in figure 13, all RMS errors are obtained from eq.…”

Section: Measurement Accuracymentioning

confidence: 99%

“…HIGH-performance time-to-digital converter (TDC) is the core component for time interval measurements in scientific instruments and industrial applications, such as quantum imaging and communications [1,2], automatic test equipment (ATE) [3], high-energy particle physics [4], satellite measurement and control [5], LiDAR ranging systems [6], positron emission tomography [7], hardware security [8], all-digital phase-locked loops [9], and unmanned vehicles [10], etc.…”

Section: Introductionmentioning

confidence: 99%

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Design of a high-accuracy time-to-digital converter based on dual-edge signals

et al. 2023

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Among numerous time-to-digital converters (TDC), tapped delay line (TDL) is the most commonly used architecture. However, its dead time of more than two cycles is inefficient for applications with high measurement rates. Limited by the device process, the delay of each cell in the TDL exhibits a random and uneven distribution, degrading the linearity of the TDC. In this study, a dual-edge TDL structure is proposed. By improving original pulse-holding circuit, the propagated signal injected into the fine measurement chain is alternately switched between rising and falling edge signals to decrease the dead time to one cycle. The nonlinearity problem is alleviated by an enhanced tapped sampling sequence circuit. A dual-edge “1” count encoder is introduced to effectively simplify the difficulty of addressing the bubble problem. Bit-by-bit calibration and a moving average filter are adopted to improve accuracy. The proposed scheme has been verified on a Xilinx Kintex-7 FPGA platform. The resolution (least significant bit, LSB1) is 12.07 ps when the propagated signal in the TDL is the rising edge. The differential nonlinearity (DNL) is [-0.81,0.93] LSB1, and the integral nonlinearity (INL) is between [-2.33,2.19] LSB1. At the falling edge, the resolution (LSB0) is 11.90 ps, between [-0.73,0.98] LSB0 and [-2.46,1.83] LSB0 for DNL and INL, respectively. In addition, the accuracy reaches 15.25 ps after multiple measurements for different time intervals separately.

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Section: Measurement Accuracymentioning

confidence: 99%