Mixed-criticality transactional memory controller for embedded systems

Owda, Zaher; Obermaisser, Roman

doi:10.1109/indin.2016.7819142

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Cited by 2 publications

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“…• [148] describes a priority-based HTM controller designed specifically for mixed-criticality systems, with support for timing analysis, selection of conflict resolution algorithms and techniques for fault propagation avoidance.…”

Section: Memorymentioning

confidence: 99%

Multi-core Devices for Safety-critical Systems

et al. 2020

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Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

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Section: Memorymentioning

confidence: 99%