Mixed capacitor switching scheme for SAR ADC with highest switching energy efficiency

Abstract

A high energy-efficiency mixed capacitor switching scheme is proposed for the successive approximation register (SAR) analogue-to-digital converter (ADC). The new switching scheme combines a new switching method, monotonic switching method and split-capacitor technique. The new switching method achieves no switching energy consumption until the fourth comparison, and the low-power monotonic switching method is utilised for the remaining comparisons. Moreover, fewer bit capacitors are needed at the same resolution because of the split-capacitor technique. The proposed method achieves a 99.4% reduction in switching energy when compared with the conventional SAR architecture.

Low‐power successive approximation ADC using split‐monotonic capacitive DAC

“…The SA-ADC, which consists of a capacitive-array digitalto-analogue converter (DAC), a comparator, and a control logic circuit, uses a successive approximation algorithm to determine the output digital bits corresponding to the input analogue sample. In order to reduce the silicon area and energy consumption of the SA-ADC, in the literature, several capacitive DAC architectures and switching techniques have been reported [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. Considering the same unit capacitor size for all the structures, the monotonic switching technique [6] has achieved a power reduction of 81%, when compared with the conventional counterpart.…”

Energy‐efficient capacitor‐swapping reset scheme with MSB‐split DAC for SAR ADCs

“…In capacitive DAC (CDAC)-based SAR ADCs, the switching energy consumed by CDAC is considerable during a SAR conversion cycle. Recently, various techniques have been developed to reduce the switching energy of CDAC arrays [1][2][3][4][5][6][7][8]. Compared with the conventional scheme, the V cm -based scheme [2], the switchback scheme [3] and Zhu [4] achieve a switching energy reduction of 87.5, 90.6 and 98.8%, respectively.…”

“…During the second bit cycle, the LSB sub-array on the higher voltage potential side is changed to '1/2' while the MSB sub-array on the lower voltage potential side is set to '1/2', where '1/2' represents a third voltage reference V cm that equals to half of the voltage reference V ref . This operation consumes zero switching energy according to Ni et al [8]. During the third bit cycle, the side with […”

Charge‐dumping switching scheme for successive‐approximation‐register analogue‐to‐digital converters

“…The techniques in [1][2][3][4][5][6][7][8][9] employ top-plate sampling to avoid switching power in the first bit cycle. Charge recycling is utilised in [1,[3][4][5][6][7] to avoid power consumption in the second cycle. V CM -based switching in the last cycle [1,4,5] generates one additional bit, thus halving the total DAC capacitance and reducing power.…”

“…where n is the number of bits, C is the unit capacitor, and V REF is the reference voltage. Note that the reference voltage in this Letter is only one-fourth of those in [1][2][3][4][5][6][7][8][9][10].…”