Mixed body-bias techniques with fixed Vt and Ids generation circuits

Sumita, M.; Sakiyama, Shiro; Kinoshita, Masayoshi; Araki, Y.; Ikeda, Y.; Fukuoka, Kazuki

doi:10.1109/icicdt.2005.1502638

Cited by 25 publications

(13 citation statements)

References 2 publications

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“…Hence, onchip real-time monitoring circuit is needed to trace the optimal VBB under the device variation. Some precedent works for monitoring and fixing die-to-die variation by body biasing are reported [3][4][5]. Most of them use drive current monitors, however.…”

Section: Optimal Vbb Scan Under Gidl Effectmentioning

confidence: 98%

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Fujii

Suzuki

Notani

et al. 2008

ESSCIRC 2008 - 34th European Solid-State Circuits Conference

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This paper proposes on-chip leakage monitor circuit to scan optimal reversed body-biasing voltage (VBB) at which leakage current becomes minimal under gate induced drain leakage (GIDL) effect. The proposed circuit determines optimal VBB from the differential measurement of two replica circuit without absolute leakage current measurement. We fabricated this leakage monitor circuit in a 45nm-CMOS process. Measurement results shows 0.1 V resolution of VBB optimization.

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Section: Optimal Vbb Scan Under Gidl Effectmentioning

confidence: 98%

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Fujii

Suzuki

Notani

et al. 2008

ESSCIRC 2008 - 34th European Solid-State Circuits Conference

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“…However, their solution also requires voltage levels higher than the core V DD and lower than V SS , mainly for generating RBB, and also for this design, the FBB voltage is V DD -dependent. Sumita et al presented another ABB generator [5]. However, it has similar constraints as the one proposed in [4].…”

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

A forward body bias generator for digital CMOS circuits with supply voltage scaling

Meijer

Gyvez

Kup

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Meijer, R.I.M.P.; Pineda de Gyvez, J.; Kup, B.; Uden, van, B.; Bastiaansen, P.; Lammers, M.; Vertregt, M. Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim.

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“…However, the optimal timing control or voltage levels would be difficult to design against process variations. Body-biasing schemes with replica monitor circuits were reported [8] [9]. These methods mainly reduce the leakage current in the stand-by mode while restoring the data retention margin.…”

Section: Introductionmentioning

confidence: 98%

Process Variation Tolerant SRAM Cell Design

Varanasi

Mandavilli

2011

2011 International Symposium on Electronic System Design

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One of the major hurdles in the design of Static Random Access Memory (SRAM) cell is the ever increasing process variations. To counter this researchers have proposed various bit-cell and non-bit-cell oriented designs. However, the proposed techniques require additional circuitry and hence account for large area overhead. In this paper we propose the use of rise time of word-line signal as a measure to reduce the impact of the process variations on the SRAM cells. Simulation results show that using a higher rise time resulted in drastic reduction in the number of cells that fail to read or write. Number of cells that can successfully write or read improved from 82% to 98.2% and 90% to 98.8% respectively. However, there is some speed penalty to achieve this.

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Mixed body-bias techniques with fixed Vt and Ids generation circuits

Cited by 25 publications

References 2 publications

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

A forward body bias generator for digital CMOS circuits with supply voltage scaling

Process Variation Tolerant SRAM Cell Design

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