Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Philip, J.; Zia, Aamir; Erdogan, Okan; Belemjian, Paul M.; Kim, Jin-Woo; Chu, Michael; Kraft, R.P.; McDonald, J. F.; Bernstein, K.

doi:10.1109/jproc.2008.2007472

Cited by 56 publications

(27 citation statements)

References 26 publications

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“…3D integration has become the alternative technology to continue producing higher performance electronic devices stacking of multiple dies or wafers interconnected using through silicon vias (TSVs). For future manycore architecture with Network on Chip (NoC) architecture, 3D IC technology is very important in the sense that it provides many advantages which are not available through traditional 2D architecture design methods such as higher memory bandwidth [2] and higher inter-core communication performance through vertical connections [3]. Design space exploration is one of the important things to be concerned helping designers to evaluate different architectural implementations possibility before it is implemented in real hardware and is particularly important for 3D architecture to be able to choose the best architectural candidate with the most performance gain.…”

Section: Introductionmentioning

confidence: 99%

Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance

Jabbar

M'zah

Hammami

et al. 2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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The need for higher performance devices to enable more complex applications continues to drive the growth of electronic design especially in the mobile markets. 3D integration is one of the feasible technologies to increase the system's performance and device integration by stacking multiple dies interconnected using through silicon vias (TSV). NoC-based Multiprocessor System on Chip (MPSoC) architecture has become the primary technology to provide higher performance to support more complex applications. In this paper, we perform an exploration and analysis of 2D EDA tool parameters impact on the 3D MPSoC architectures (3D Mesh MPSoC and heterogeneous 3D MPSoC stacking) performance in terms of timing and power characteristics. Exploration results show that the 2D EDA tool parameters have strong impact on the timing performance compared with power consumption. Furthermore, it is also shown that heterogeneous 3D MPSoC architecture has less footprint area, higher speed and less power consumption compared with 3D Mesh MPSoC for the same number of processing elements suggesting that it is a better design approach considering the limitation capability of 2D EDA tools for 3D design.

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Section: Introductionmentioning

confidence: 99%

Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance

Jabbar

M'zah

Hammami

et al. 2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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“…3-D integration also provides unique advantages to develop highly heterogeneous systems where diverse functions such as analog/RF based communication, sensing circuitry, digital data processing blocks, and sensors are merged in a monolithic fashion [3,7,8], as illustrated in Fig a processor and memory has grown due to significantly different scaling characteristics [9,10]. This issue has been partly relieved with the introduction of multilevel cache with different size and speed [11]. The growing disparity, however, remains as a primary concern.…”

Section: Introductionmentioning

confidence: 99%

Power Distribution in TSV-Based 3-D Processor-Memory Stacks

Satheesh

Salman

2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Electrical Engineering Stony Brook University 2012Three primary techniques for manufacturing through silicon vias (TSVs), viafirst, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this work. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to number of TSVs and decoupling capacitance.iii To my dearest parents, Jayashree Krishnamurthy and Satheesh Lakshminarayana.

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“…Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging approach to addressing issue of memory wall (i.e., the difference in speeds between the processor and memory) [1], [2]. For example, some processormemory stacked 3D chips have been presented recently [3], [4].…”

Section: Introductionmentioning

confidence: 99%

On test and repair of 3D random access memory

2012

17th Asia and South Pacific Design Automation Conference

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The three-dimensional (3D) random access memory (RAM) using through-silicon via (TSV) has been considered as a promising approach to overcome the memory wall. However, cost and yield are two key issues for volume production of 3D RAMs, and yield enhancement increasingly requires test techniques. In this paper, we first introduce issues and existing techniques for the testing and yield enhancement of 3D RAMs. Then, a built-in selfrepair (BISR) technique for 3D RAM using global redundancy is presented. According to the redundancy analysis results of each die with the BISR circuit, the die-to-die (d2d) and wafer-to-wafer (w2w) stacking problems are transferred to the bipartite maximal matching problem. Then, heuristic algorithms are also proposed to optimize the stacking yield.

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Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Cited by 56 publications

References 26 publications

Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance

Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance

Power Distribution in TSV-Based 3-D Processor-Memory Stacks

On test and repair of 3D random access memory

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