Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplfier

James, Diego; Kunnath, Abishek Thekkeyil; Purushothaman, A.; Sahoo, Bibhu Datta

doi:10.1109/vlsid.2018.29

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2021

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“…However, the input buffer in front of the pipelined stages should be linear enough to reduce the impact on the whole ADC performance. Besides, due to the timing skew and bandwidth mismatch between two sampling networks, the input signal sampled by the multiplying digital-to-analog converter (MDAC) and sub-ADC of the first pipelined stage can be different after removing the front-end SHA, which is called as aperture-error, may also deteriorate the perfor-mance of the pipelined ADC [18].…”

Section: Introductionmentioning

confidence: 99%

A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS

Chen¹,

Wu²,

Shen³

et al. 2021

IEICE Electron. Express

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This paper presents a 14bit 500MS/s SHA-less pipelined analog-to-digital converter (ADC) implemented in 40nm CMOS. A highlinearity pseudo-differential push-pull input buffer with an anti-oscillation technique and a nonlinear parasitism eliminate technique is proposed to stably drive the pipelined stages while keeping low distortion. Moreover, a digital controlled aperture-error calibration is also employed with offset of comparators compensated in advance. Measurement results show that the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 66.29dB and a spurious-free-dynamic-range (SFDR) of 85.62dBc at 80.1MHz input.

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Section: Introductionmentioning

confidence: 99%