MIST: an algorithm for memory miss traffic management

Abstract

Cache misses represent a major bottleneck in embedded systems performance. Traditionally, compilers optimistically treated all memory accesses as cache hits, relying on the memory controller to account for longer miss delays. Howevel; the memory controllerhas only a local view of the program, and is not able to eficiently hide the latency of these memory operations. Our compiler technique actively manages cache misses, and performs global miss trafic optimizations, to better hide the latency of the memory operations. Our memory-aware compiler scheduled several benchmarks on the TIC6211 processor architecture with a direct mapped cache, and generated an average of 61.6% improvement over the best schedule of the traditional (memory-transparent) optimizing compilel; demonstrating the utility of our miss trafic optimization approach.

Processor-memory coexploration using an architecture description language

“…As described earlier, we have already used this memory-aware ADL to generate a compiler [Grun et al 2000a] and manage the memory miss traffic [Grun et al 2000b], resulting in significantly improved performance. We performed comparative studies with the MULTI integrated development environment (IDE) version 3.5 from Green Hills Software Inc. [2003] for the MIPS R4000 processor.…”

“…Section 4 shows an example of performance improvement due to this detailed memory subsystem timing information [Grun et al 2000a]. Such aggressive optimizations in the presence of efficient memory access modes (e.g., page/burst modes) and cache hierarchies [Grun et al 2000b] are only possible due to the explicit representation of the detailed memory architecture. We generate memory simulator (shown shaded in Figure 1) that is integrated into the SIMPRESS ] simulator, allowing for detailed feedback on the memory subsystem architecture and its match to the target applications.…”

Reuse Distance-Based Cache Hint Selection

“…The references rX , rZ , rY and rW are not part of a reuse pair, since memory lines W, X, Y and Z are accessed only once in the stream. Reuse pair r 1 A , r 2 A has reuse distance 4, while the reuse pair r 2 A , r 3 A has reuse distance 0. The forward reuse distance of r 1 A is 4, its backward reuse distance is ∞.…”

New directions in compiler technology for embedded systems

“…Then, the technique was extended so that it can be well incorporated into loop tiling. More recently, Grun et al presented a new compiler optimization which uses accurate memory access timing information for both cache hits and misses, and schedules instructions so that memory accesses are efficiently overlapped [23].…”