Miss rate prediction across all program inputs

Zhong, Yutao; Dropsho, Steven; Ding, Chen

doi:10.1109/pact.2003.1238004

Cited by 43 publications

(63 citation statements)

References 25 publications

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“…Our PIN tool records profiles in between every pair of barrier calls-i.e., per parallel region. 1 Multiple loops can occur within a single parallel region so this does not isolate all parallel loops, but it is sufficient for our study.…”

Section: A Profilingmentioning

confidence: 99%

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Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs

Yeung

2011

2011 International Conference on Parallel Architectures and Compilation Techniques

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Abstract-Reuse distance (RD) analysis is a powerful memory analysis tool that can potentially help architects study multicore processor scaling. One key obstacle though is multicore RD analysis requires measuring concurrent reuse distance (CRD) profiles across thread-interleaved memory reference streams. Sensitivity to memory interleaving makes CRD profiles architecture dependent, preventing them from analyzing different processor configurations. For loop-based parallel programs, CRD profiles shift coherently to larger CRD values with core count scaling because interleaving threads are symmetric. Simple techniques can predict such shifting, making the analysis of numerous multicore configurations from a small set of CRD profiles feasible. Given the ubiquity and scalability of loop-level parallelism, such techniques will be extremely valuable for studying future large multicore designs. This paper investigates using RD analysis to efficiently analyze multicore cache performance for loop-based parallel programs, making several contributions. First, we provide indepth analysis on how CRD profiles change with core count scaling. Second, we develop techniques to predict CRD profile scaling, in particular employing reference groups [1] to predict coherent shift, and evaluate prediction accuracy. Third, we show core count scaling only degrades performance for lastlevel caches (LLCs) below 16MB for our benchmarks and problem sizes, increasing to 64-128MB if problem size scales by 64x. Finally, we apply CRD profiles to analyze multicore cache performance. When combined with existing problem scaling prediction, our techniques can predict LLC MPKI to within 11.1% of simulation across 1,728 configurations using only 36 measured CRD profiles.

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Section: A Profilingmentioning

confidence: 99%

“…We employ reference groups [1], a technique previously used to predict RD profiles across problem scaling, to predict coherent shifting. We also propose uniformly distributing the portion of CRD profiles associated with shared references to predict spreading.…”

Section: Introductionmentioning

confidence: 99%

Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs

Yeung

2011

2011 International Conference on Parallel Architectures and Compilation Techniques

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“…Previous work on computing cache miss predictions from memory reuse distance information has explored approaches that associate reuse distance data with either individual references [9], [13], groups of related references from the same loop [14], or an entire application [23]. Associating reuse distance data with a section of code, be it a reference, a loop or an entire application, is sufficient for computing the number of cache misses incurred by that piece of code.…”

Section: Understanding Data Reuse Patternsmentioning

confidence: 99%

“…These include investigating memory hierarchy management techniques [3], [16], characterizing data locality in program executions for individual program inputs [4], [7], and using memory reuse distance data from training runs to predict cache miss rate for other program inputs [9], [13], [23].…”

Section: Introductionmentioning

confidence: 99%

Pinpointing and Exploiting Opportunities for Enhancing Data Reuse

Marin

Mellor-Crummey

2008

ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and Software

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Abstract-The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than memory. Traditional performance tools typically collect or simulate cache miss counts or rates and attribute them at the function level. While such information identifies program scopes that exhibit a large cache miss rate, it is often insufficient to diagnose the causes for poor data locality and to identify what program transformations would improve memory hierarchy utilization. This paper describes an approach that uses memory reuse distance to identify an application's most significant memory access patterns causing cache misses and provide insight into ways of improving data reuse. Unlike previous approaches, our tool combines (1) analysis and instrumentation of fully optimized binaries, (2) online analysis of reuse patterns, (3) fine-grain attribution of measurements and models to statements, loops and variables, and (4) static analysis of access patterns to quantify spatial reuse. We demonstrate the effectiveness of our approach for understanding reuse patterns in two scientific codes: one for simulating neutron transport and a second for simulating turbulent transport in burning plasmas. Our tools pinpointed opportunities for enhancing data reuse. Using this feedback as a guide, we transformed the codes, reducing their misses at various levels of the memory hierarchy by integer factors and reducing their execution time by as much as 60% and 33%, respectively.

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“…A trace may not represent the program behavior on other inputs, and a trace may be too large to be analyzed. For many programs, earlier work has shown that the temporal locality follows a predictable pattern and the (cache miss) behavior of all program inputs can be predicted by examining medium-size training runs [14,15,26,34,44]. In this paper, we use a medium-size input for each program.…”

Section: Introductionmentioning

confidence: 99%

The Potential of Computation Regrouping for Improving Locality

Ding

Orlovich

Proceedings of the ACM/IEEE SC2004 Conference

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Improving program locality has become increasingly important on modern computer systems. An effective strategy is to group computations on the same data so that once the data are loaded into cache, the program performs all their operations before the data are evicted. However, computation regrouping is difficult to automate for programs with complex data and control structures.This paper studies the potential of locality improvement through trace-driven computation regrouping. First, it shows that maximizing the locality is different from maximizing the parallelism or maximizing the cache utilization. The problem is NP-hard even without considering data dependences and cache organization. Then the paper describes a tool that performs constrained computation regrouping on program traces. The new tool is unique because it measures the exact control dependences and applies complete memory renaming and re-allocation. Using the tool, the paper measures the potential locality improvement in a set of commonly used benchmark programs written in C.

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Miss rate prediction across all program inputs

Abstract: Abstract

Cited by 43 publications

References 25 publications

Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs

Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs

Pinpointing and Exploiting Opportunities for Enhancing Data Reuse

The Potential of Computation Regrouping for Improving Locality

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