Miss penalty reduction using bundled capacity prefetching in multiprocessors

Abstract

Abstract

Cache memory behavior of advanced PDE solvers

“…However, the coherence and data traffic on the interconnect increase heavily compared to a non-prefetching protocol. We show that by using the bundling technique, previously published in [28], the coherence traffic can be kept under control.…”

“…The snoop lookups can be largely reduced in sequential prefetching using the bundling technique presented in a previous publication [28]. Bundling lumps the original read request together with the prefetch requests to the consecutive addresses.…”

“…databases and serverapplications, since the largest market share is within this field. In these applications, the data access pattern is very unstructured and a large amount of false sharing occurs [16,28]. Popular benchmarks used when designing multiprocessors are the TPC-benchmarks [2] and the SPEC/OSG-benchmarks [1].…”

Bundling: reducing the overhead of multiprocessor prefetchers

“…Unfortunately, enlarging the cache line size is not as efficient in multiprocessors as in uniprocessors since it can lead to a large amount of false sharing and an increase in data traffic. The influence of cache line size on cache miss rate and data traffic has been studied by several authors [9], [11], [13], [26], [27]. To avoid false sharing and at the same time take advantage of spatial locality, sequential prefetching fetches a number of cache lines having consecutive addresses on a read cache miss.…”

“…None of these protocols have used piggybacking as a method of reducing the address snoops for prefetches. A simple form of bundling applied only to read transactions has previously been studied together with the capacity prefetching technique [26]. However, no evaluation of the possible performance gains of read bundling has previously been performed.…”