Mismatch Drift: A Reliability Issue for Analog MOS Circuits

Michael, Christopher; Wang, Hai; Teng, C.S.; Shibley, James; Lewicki, Larry; Shyu, C. M.; Lahri, R.

doi:10.1109/irps.1992.363277

Cited by 3 publications

(2 citation statements)

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“…Of course, if the transistors are too large, implant microuniformity variations can again increase the magnitude of the mismatch [3]. For high reliability automotive applications an additional requirement is that the matching remain constant over time [4]. In accelerated testing matching was unchanged when transistors were similarly biased.…”

Section: Introductionmentioning

confidence: 99%

Zero Defectivity Dual Gate Processing

Towner¹,

Naughton²,

Lappan³

2007

ECS Trans.

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A mixed-signal automotive device manufactured in a dual gate process historically had sporadic yields. Problems were associated with analog failures, including the temperature sense circuit, load dump trip levels, comparators and the 8MHz oscillator. These issues related to p-mos devices with common mode inputs <1.5V. The only anomaly observed at electrical test was in the threshold voltage matching of a particular size of transistor pairs. When 100% testing of these scribe line monitors was performed there were many random failures, with higher probability around the perimeter of the wafer. The magnitude of the offset was consistent with a 2nm difference in gate oxide thickness. Darkfield inspection following etchback of oxide from standard gate regions showed water spotting and damage to active areas. No defects were observed following the introduction of a 10sec oxygen plasma treatment prior to oxide etchback. This change coincided with improved yields and the elimination of the analog failures.

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Section: Introductionmentioning

confidence: 99%

Zero Defectivity Dual Gate Processing

Towner¹,

Naughton²,

Lappan³

2007

ECS Trans.

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“…Implicit to this observation is the assumption that improved unstressed (T=O) matching will be preserved during normal circuit operation. Individual MOSFETs in analog components such as current mirrors age unequally during circuit operation and the amount of parameter drift varies with the particular circuit configuration that is used [2]. The aged mismatch is brought about by hot carrier stress that causes interface trap generation and trapped charges in the oxide.…”

Section: Introductionmentioning

confidence: 99%

Influence of passivation anneal position on metal coverage dependent mismatch and hot carrier reliability

Chetlur

Sen²,

Harris³

et al. 1999

Proceedings of the 1999 7th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.99TH83

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Prolonged higher temperature passivation anneals are purported to minimise metal coverage induced transistor mismatch in multi-level-metal (MLM) CMOS circuits.However, process changes that improve unstressed ('PO) device matching do not necessarily lead to better matching under hot carrier stress. As a result, matched transistor parameters can drift disproportionately during circuit operation and increase mismatch. Here, we demonstrate that the popular method of improving mismatch by increasing the post-cap final passivation anneal temperature and time can adversely impact the dc hot carrier ageing (HCA) behaviour. By changing the position of the passivation anneal in the fabrication process flow, the device is made more robust to hot carrier ageing while improving transistor matching.

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Composite n-MOSFET for submicrometre circuits

Hwang

Forbes

1993

Electron. Lett.

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Mismatch Drift: A Reliability Issue for Analog MOS Circuits

Cited by 3 publications

References 0 publications

Zero Defectivity Dual Gate Processing

Zero Defectivity Dual Gate Processing

Influence of passivation anneal position on metal coverage dependent mismatch and hot carrier reliability

Composite n-MOSFET for submicrometre circuits

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