Mismatch characterisation of chip interconnect resistance

Deveugele, Jurgen; Yao, Libin; Steyaert, Michiel; Sansen, Willy

doi:10.1109/icmts.2005.1452259

Cited by 4 publications

(1 citation statement)

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“…For example, [14] and [15] proposes test structures for characterizing wire resistance mismatch. Resistance measurement and analysis techniques for linewidth and step variation are described in [16] and [17].…”

Section: Introductionmentioning

confidence: 99%

Measuring Power Distribution System Resistance Variations

Helinski

Plusquellic

2008

IEEE Trans. Semicond. Manufact.

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Metal resistance variations in back-end-of-line processes can be significant, particularly during process bring-up. In this paper, we propose a simple method to measure resistance variations in the power distribution system (PDS) eof an IC. Our technique utilizes the PDS because it is an existing distributed resource in all ICs and provides a means of characterizing resistance in the context of the actual circuit design. By applying a set of tests using small on-chip support circuits attached to the PDS, the resistance of components of the PDS can be obtained from the solution to a set of simultaneous equations. The results from hardware experiments involving two sets of test chips fabricated in an IBM 65-nm technology show significant changes in the resistance variation of some components of the PDS as the process evolved.

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