Minimum propagation delays in VLSI

Mead, C. A.; Rem, Martin

doi:10.1109/jssc.1982.1051810

Cited by 84 publications

(13 citation statements)

References 2 publications

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“…Several methods can be used. The simplest method is the Sutherland method [4], directly deduced from the Mead's optimization rule of an ideal inverter array [15]: the same delay constraint is imposed on each element of the path. If this supplies a very fast method for distributing the constraint, this is at the cost of an over sizing of the gates with an important logical weight value…”

Section: Constraint Distribution: Constant Sensitivity Methodsmentioning

confidence: 99%

“…The definition of the lower bound has been the subject of numerous proposals. For ideal inverters without parasitic loading the minimum is reached when all the inverters have an equal tapering factor that can be easily calculated from a first order delay representation [7,15]. Applying the explicit representation given in (1) to a bounded combinatorial path, the inferior delay bound is easily obtained by canceling the de-rivative of the path delay with respect to the input capacitance of the gates.…”

Section: Constraint Feasibilitymentioning

confidence: 99%

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Performance Metric Based Optimization Protocol

Michel

Verle

Maurine

et al. 2004

Lecture Notes in Computer Science

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Optimizing digital designs implies a selection of circuit implementation based on different cost criteria. Post-processing methods such as transistor sizing, buffer insertion or logic transformation can be used for optimizing critical paths to satisfy timing constraints. However most optimization tools are not able to select between the different optimization alternatives and have high CPU execution time.In this paper, we propose an optimization protocol based on metrics allowing to characterize a path and to select the best optimization alternative. We define a way to characterize the design space of any circuit implementation. Then we propose a constraint distribution method allowing constraint satisfaction at nearly minimum area. This quasi optimal tool is implemented in an optimization tool (POPS) and validated by comparing the area necessary to satisfy delay constraints applied to various benchmarks (ISCAS'85) to that resulting from an industrial tool.

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Section: Constraint Distribution: Constant Sensitivity Methodsmentioning

confidence: 99%

Section: Constraint Feasibilitymentioning

confidence: 99%

Performance Metric Based Optimization Protocol

Michel

Verle

Maurine

et al. 2004

Lecture Notes in Computer Science

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“…To estimate the propagation delay for the various designs, we adopt a simple and well-known model [10]. We assume the use of square areas for the layout of cells and the entire array, making the longest wire length proportional to k .…”

Section: Design Trade-offs and Optimalitymentioning

confidence: 99%

“…with c 1 , c 2 , and c 3 being technology-dependent constants [10]. We have derived these constants for the following analysis using a 0.8 µm CMOS double-metal technology with the second layer of metal for interconnections.…”

Section: Design Trade-offs and Optimalitymentioning

confidence: 99%

Data-driven control scheme for linear arrays: application to a stable insertion sorter

Parhami

Kwai²

1999

IEEE Trans. Parallel Distrib. Syst.

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Abstract-We present a strategy for designing stable insertion sorters based on linear arrays with data-driven control. The novelty of our approach lies in each data item carrying a control tag to specify how it is to be operated upon by a receiving cell and in performing two parallel comparisons within each cell. To assure first-in/first-out handling of equal key values, some data items must be marked to reflect their past histories. Such marking is conveniently carried out by modifying the data item's control tag. It is the combination of the above features that allows us to derive the first single-cycle priority queue that operates in fully pipelined mode, with no broadcasting of data values or control signals. By performing more than two parallel comparisons in each cell, the VLSI implementation cost of our stable sorter can be reduced. We show that highly cost-effective designs can be obtained by selecting an optimal cell size in terms of the number of comparators it contains.

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“…Because of the improvements of this technology, circuits could be made smaller and smaller. It turned out, however, that if all characteristic dimensions of a circuit are scaled down by a certain factor, including the clock period, delays in long wires do not scale down proportional to the clock period [14,22]. As a consequence, some VLSI designs when scaled down may no longer work properly anymore, because delays for some computations have become larger than the clock period.…”

mentioning

confidence: 99%

A formal approach to designing delay-insensitive circuits

Ebergen

1991

Distrib Comput

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A method for designing delay-insensitive circuits is presented based on a simple formalism. The communication behavior of a circuit with Its envlronmenf is speclfied by a regular expresslon-llke program. Based on formal manipulations this program is then transformed into a delay·insensltlve connection of basic elements realizing the specified circuit. The notion 01 delay-lnsensitlvlty Is concisely formalized.

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Minimum propagation delays in VLSI

Cited by 84 publications

References 2 publications

Performance Metric Based Optimization Protocol

Performance Metric Based Optimization Protocol

Data-driven control scheme for linear arrays: application to a stable insertion sorter

A formal approach to designing delay-insensitive circuits

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