Minimizing Vias and Wirelength in 3-D IC Floorplanning

Banerjee, Suchandra; Roy, Suchismita; Bhattacharya, Archita

doi:10.1109/iespc.2019.8902373

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2019 2nd International Conference on Innovations in Electronics, Signal Processing and Communication (IESC) 2019

DOI: 10.1109/iespc.2019.8902373

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Minimizing Vias and Wirelength in 3-D IC Floorplanning

Suchandra Banerjee

Suchismita Roy

Archita Bhattacharya

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Minimizing Vias and Wirelength in 3-D IC Floorplanning

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References 15 publications

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