Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling

Eichenberger, Alexandre E.; Davidson, Edward S.; Abraham, Santosh G.

doi:10.1007/bf03356744

Cited by 20 publications

(14 citation statements)

References 22 publications

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“…Therefore a great amount of work tries to schedule the instructions of a loop (under resource and time constraints) such that the resulting code does not use more than R values simultaneously alive. Usually they look for a schedule that minimises the stormain_siralina.tex; 19/12/2011; 10:42; p.2 age requirement under a fixed scheduling period while considering resource constraints (Eichenberger et al, 1996;Fimmel and Muller, 2001;Janssen, 2001;de Dinechin, 1996). Some fundamental results that analyse the tradeoff between memory (register pressure) and parallelism in one-dimensional cyclic instruction schedules are published in (Touati, 2007).…”

Section: Related Workmentioning

confidence: 99%

SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling

2010

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Abstract. In this paper, we study the general problem of one-dimensional periodic task scheduling under storage requirement, irrespective of machine constraints. We have already presented in (Touati and Eisenbeis, 2004) a theoretical framework that allows an optimal optimisation of periodic storage requirement in a cyclic schedule. Since our optimization problem is NP-hard (Touati, 2002), solving an exact integer linear programming formulation is too expensive in practice. In this article, we propose an efficient two-steps heuristic using model's properties that allows fast computation times while providing highly satisfactory results. This method includes the solution of an integer linear program with a totally unimodular constraints matrix in first step, then the solution of a linear assignment problem. Our heuristic is implemented for an industrial compiler for embedded VLIW processors.

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Section: Related Workmentioning

confidence: 99%

SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling

2010

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“…Indeed, researchers in this area studied the special case when the scheduling period is unique and integral as done in [12] improved recently in [7]. In case of cyclic scheduling under register constraints, most of the approaches try to build a SWP schedule with a minimised MAXLIVE, see [4,6,22]. Then, in a second step, cyclic register allocation can be applied using the methods described in [9] improved later in [3].…”

Section: Related Workmentioning

confidence: 99%

Periodic register saturation in innermost loops

Touati

Mathe

2009

Parallel Computing

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This article treats register constraints in high performance embedded VLIW computing, aiming to decouple register constraints from instruction scheduling. It extends the register saturation (RS) concept to periodic instruction schedules, i.e., software pipelining (SWP). We formally study an approach which consists in computing the exact upper-bound of the register need for all the valid SWP schedules of an innermost loop (without overestimation), independently of the functional unit constraints. We call this upper-limit the periodic register saturation (PRS) of the data dependence graph (DDG). PRS is well adapted to situations where spilling is not a favourite solution for reducing register pressure compared to ILP scheduling: spill operations request memory data with a higher energy consumption. Also, spill code introduces unpredictable cache effects and makes Worst-Case-ExecutionTime (WCET) estimation less accurate. PRS is a computer science concept that has many possible applications. First, it provides compiler designers new ways to generate better codes regarding register optimisation by avoiding useless spilling. Second, its computation can help architectural designers to decide about the most suitable number of available registers inside an embedded VLIW processor; such architectural decision can be done with full respect to instruction level parallelism extraction, independently of the chosen functional units configuration. Third, it can be used to verify prior to instruction scheduling that a code does not require spilling. In this paper, we write an appropriate mathematical formalism for the problem of PRS computation and reduction in the case of loops where data dependence graphs may be cyclic. We prove that PRS reduction is NP-hard and we provide optimal and approximate methods. We have implemented our methods, and our experimental results demonstrate the practical usefulness and efficiency of the PRS approach.

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“…We can use either loop unrolling [2], inserting move operations [7], or a hardware rotating register file when available [13] 2 . Therefore, a great amount of work tries to schedule a loop such that it does not use more than R values simultaneously alive [8,22,12,14,11,4,15,6,9]. In this paper we directly work on the loop DDG and modify it in order to satisfy the register constraints for any further subsequent software pipelining pass.…”

Section: Introductionmentioning

confidence: 99%

Early Control of Register Pressure for Software Pipelined Loops

Touati

Eisenbeis

2003

Lecture Notes in Computer Science

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Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at first step without assuming a schedule lacks the information of interferences between variable lifetime intervals. Thus, the register allocator may introduce an excessive amount of false dependences that reduce dramatically the ILP (Instruction Level Parallelism). We present a new framework for controlling the register pressure before software pipelining. This is based on inserting some anti-dependences edges (register reuse edges) labeled with reuse distances, directly on the data dependence graph. In this new graph, we are able to guarantee that the number of simultaneously alive variables in any schedule does not exceed a limit. The determination of register and distance reuse is parameterized by the desired critical circuit ratio (MII) as well as by the register pressure constraints -either can be minimized while the other one is fixed. After scheduling, register allocation is done cyclically on conventional register sets or on rotating register files. We give an optimal exact model, and another approximative one that generalizes the Ning-Gao [12] buffer optimization heuristics.

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Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling

Cited by 20 publications

References 22 publications

SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling

SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling

Periodic register saturation in innermost loops

Early Control of Register Pressure for Software Pipelined Loops

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