Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding

Abstract

Piecewise polynomial interpolation is a well-established technique for hardware function evaluation. The paper describes a novel technique to minimize polynomial coefficients wordlength with the aim of obtaining either exact or faithful rounding at a reduced hardware cost. The standard approaches employed in literature subdivide the design of piecewise-polynomial interpolators into three steps (coefficients calculation, coefficients quantization and arithmetic hardware optimization) and estimate conservatively the overall approximation error as the sum of the error components arising in each step. The proposed technique, using Integer Linear Programming (ILP), optimizes the polynomial coefficients taking into account all error components simultaneously. This gives two advantages. Firstly, we can obtain exactly rounded approximations; secondly, for faithfully rounded interpolators, we avoid any overdesign due to pessimistic assumptions on error components, optimizing in this way the resulting hardware. The proposed ILP based algorithm requires an acceptable CPU time (from few seconds to tens of minutes) and is suited for approximations up to, maximum, 24 input bits. The results compare favorably with previously published data. We present synthesis results in 28 nm and 90 nm CMOS technologies, to further assess the effectiveness of the proposed approach

High performance correctly rounded math libraries for 32-bit floating point representations

“…Our goal is to get the best possible performance within a given storage budget for piecewise polynomials (i.e., number of sub-domains when we split the range of reduced inputs). Hence, we used the RLibm-32 to generate piecewise polynomials such that the degree of each polynomial was less than or equal to 8 and the number of sub-domains was less than or equal to 2 14 . The output compensation for ℎ( ), ℎ( ), ( ), and ( ) involves two elementary functions.…”

“…If it does, then we widen the reduced interval by replacing each with the preceding value. We repeat the process until the result of output compensation using the preceding values no longer produces a value in [ , ℎ] (lines [12][13][14][15]. This procedure to compute the lower bound can be efficiently implemented by performing binary search between and the minimum representable value.…”

“…If we successfully generate a polynomial Ψ that satisfies all constraints in the sample, then we check whether this polynomial satisfies all constraints in Δ (line [10][11][12][13][14][15]. If Ψ satisfies all constraints, then we return the polynomial (line 7).…”

Precision analysis with analytical bit‐width optimisation process for linear circuits with feedbacks

“…However, in this paper, we target MM and performed specific bitwidth allocation separately for each source of error, which gives more robustness to our method. Authors in [1,2,[17][18][19][20][21][22][23] propose specified methods for feedforward circuits. Moreover, authors in [18][19][20][21][22][23] target BWO of arithmetic circuits specified by polynomials.…”

“…Authors in [1, 2, 17–23] propose specified methods for feed‐forward circuits. Moreover, authors in [18–23] target BWO of arithmetic circuits specified by polynomials. Obviously, circuits with feedbacks need specific approach to consider the complication added by feedback loops.…”